On Mon, 2016-10-10 at 10:52 -0500, Dinh Nguyen wrote:
From: Dinh Nguyen dinguyen@opensource.altera.com
In order for SDRAM ECC to work correctly, the SDRAM needs to get zero'd which enables the ECC bit. By using the PL330 DMA to fill the SDRAM with zeroes, the operation is completed in ~1.2 seconds, versus ~14 seconds with a memset.
Signed-off-by: Dinh Nguyen dinguyen@opensource.altera.com
arch/arm/mach-socfpga/include/mach/reset_manager.h | 21 ++++++++++++++++ arch/arm/mach-socfpga/include/mach/sdram.h | 2 ++ arch/arm/mach-socfpga/spl.c | 8 +++++++ arch/arm/mach-socfpga/wrap_sdram_config.c | 28 ++++++++++++++++++++++ configs/socfpga_cyclone5_defconfig | 2 ++ 5 files changed, 61 insertions(+)
[..]
diff --git a/arch/arm/mach-socfpga/wrap_sdram_config.c b/arch/arm/mach-socfpga/wrap_sdram_config.c index 31cc7de..dfa6423 100644 --- a/arch/arm/mach-socfpga/wrap_sdram_config.c +++ b/arch/arm/mach-socfpga/wrap_sdram_config.c @@ -5,8 +5,10 @@ */
#include <common.h> +#include <dma.h> #include <errno.h> #include <asm/arch/sdram.h> +#include <asm/pl330.h>
/* Board-specific header. */ #include <qts/sdram_config.h> @@ -310,3 +312,29 @@ const struct socfpga_sdram_misc_config *socfpga_get_sdram_misc_config(void) { return &misc_config; }
+#if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN == 1) +/* init the whole SDRAM ECC bit */ +void sdram_ecc_init(void) +{
- struct pl330_transfer_struct pl330;
- u8 pl330_buf[2000];
Would need size of 2500 if the SDRAM size is 2GB
Thanks Chin Liang