On Dec 13, 2010, at 8:12 PM, Paul Gortmaker wrote:
On Mon, Dec 13, 2010 at 4:06 PM, Becky Bruce beckyb@kernel.crashing.org wrote:
Correct initdram to use phys_size_t to represent the size of dram; instead of changing this all over the place, and correcting all the other random errors I've noticed, create a common initdram that is used by all non-corenet 85xx parts. Most of the initdram() functions were identical, with 2 common differences:
- DDR tlbs for the fixed_sdram case were set up in initdram() on
some boards, and were part of the tlb_table on others. I have changed them all over to the initdram() method - we shouldn't be accessing dram before this point so they don't need to be done sooner, and this seems cleaner.
- Parts that require the DDR11 erratum workaround had different
implementations - I have adopted the version from the Freescale errata document. It also looks like some of the versions were buggy, and, depending on timing, could have resulted in the DDR controller being disabled. This seems bad.
Having #1 and #2 each as standalone commits might have been useful as extra bisection points, in the event that anyone runs into problems -- but I suspect that is a lot of respin work, and hopefully Things Just Work for most people.
I thought about that, but it turns out that creates a ton of patchery than then just gets whacked out.
The only other thing I noticed was that...
+/* Common ddr init for non-corenet fsl 85xx platforms */ +#ifndef CONFIG_FSL_CORENET +phys_size_t initdram(int board_type) +{
phys_size_t dram_size = 0;+#if defined(CONFIG_DDR_DLL)
{ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);unsigned int x = 10;unsigned int i;/** Work around to stabilize DDR DLL*/out_be32(&gur->ddrdllcr, 0x81000000);asm("sync;isync;msync");udelay(200);while (in_be32(&gur->ddrdllcr) != 0x81000100) {setbits_be32(&gur->devdisr, 0x00010000);for (i = 0; i < x; i++);clrbits_be32(&gur->devdisr, 0x00010000);x++;}}+#endif
+#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD)
dram_size = fsl_ddr_sdram();+#else
dram_size = fixed_sdram();+#endif
dram_size = setup_ddr_tlbs(dram_size / 0x100000);dram_size *= 0x100000;+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
/** Initialize and enable DDR ECC.*/ddr_enable_ecc(dram_size);+#endif
...right here, the 8540EVAL board bailed out if RAMBOOT was set, thus bypassing sdram_init. So this won't strictly match the old behaviour on at least that board. Maybe it makes sense to just gut the rest of the RAMBOOT code (if any) from boards that were doing this, since I believe it isn't really a globally supported (or at least encouraged) u-boot feature?
You are correct, and I missed that one (perils of the huge patchset :). However, I believe Kumar has announced he is deprecating support for that board, and I don't see any other cases of this. Yell if I've missed something else.
-Becky
I'm not anywhere near the office at the moment, but later in the week I'll see if I can find a board (or two?) to test on.
Paul.
/* Some boards also have sdram on the lbc */sdram_init();return dram_size;+} +#endif
#if CONFIG_POST & CONFIG_SYS_POST_MEMORY
/* Board-specific functions defined in each board's ddr.c */ diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c index fcef40c..10fcd24 100644 --- a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c +++ b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c @@ -9,6 +9,16 @@ #include <common.h> #include <asm/fsl_lbc.h>
+#ifdef CONFIG_MPC85xx +/* Boards should provide their own version of this if they use lbc sdram */ +void __sdram_init(void) +{
/* Do nothing */+} +void sdram_init(void) __attribute__((weak, alias("__sdram_init"))); +#endif
void print_lbc_regs(void) { int i; diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h index 17d4b31..8ceae18 100644 --- a/arch/powerpc/include/asm/fsl_ddr_sdram.h +++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h @@ -214,6 +214,19 @@ typedef struct memctl_options_s {
extern phys_size_t fsl_ddr_sdram(void);
+/*
- The 85xx boards have a common prototype for fixed_sdram so put the
- declaration here.
- */
+#ifdef CONFIG_MPC85xx +extern phys_size_t fixed_sdram(void); +#endif
+#if defined(CONFIG_DDR_ECC) +extern void ddr_enable_ecc(unsigned int dram_size); +#endif
typedef struct fixed_ddr_parm{ int min_freq; int max_freq; diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h index 82d24ab..fcf3371 100644 --- a/arch/powerpc/include/asm/fsl_lbc.h +++ b/arch/powerpc/include/asm/fsl_lbc.h @@ -16,6 +16,10 @@ #include <config.h> #include <common.h>
+#ifdef CONFIG_MPC85xx +void sdram_init(void); +#endif
/* BR - Base Registers */ #define BR0 0x5000 /* Register offset to immr */ diff --git a/board/atum8548/atum8548.c b/board/atum8548/atum8548.c index 9403e4b..d719292 100644 --- a/board/atum8548/atum8548.c +++ b/board/atum8548/atum8548.c @@ -37,8 +37,6 @@ #include <libfdt.h> #include <fdt_support.h>
-long int fixed_sdram(void);
int board_early_init_f (void) { return 0; @@ -67,7 +65,7 @@ int checkboard (void) /*************************************************************************
- fixed sdram init -- doesn't use serial presence detect.
************************************************************************/ -long int fixed_sdram (void) +phys_size_t fixed_sdram(void) { volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
@@ -96,27 +94,6 @@ long int fixed_sdram (void) } #endif /* !defined(CONFIG_SPD_EEPROM) */
-phys_size_t -initdram(int board_type) -{
long dram_size = 0;puts("Initializing\n");-#if defined(CONFIG_SPD_EEPROM)
puts("fsl_ddr_sdram\n");dram_size = fsl_ddr_sdram();dram_size = setup_ddr_tlbs(dram_size / 0x100000);dram_size *= 0x100000;-#else
puts("fixed_sdram\n");dram_size = fixed_sdram ();-#endif
puts(" DDR: ");return dram_size;-}
#if defined(CONFIG_SYS_DRAM_TEST) int testdram(void) diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c index cf92ba1..ee5b668 100644 --- a/board/freescale/mpc8536ds/mpc8536ds.c +++ b/board/freescale/mpc8536ds/mpc8536ds.c @@ -42,8 +42,6 @@
#include "../common/sgmii_riser.h"
-phys_size_t fixed_sdram(void);
int board_early_init_f (void) { #ifdef CONFIG_MMC @@ -98,25 +96,6 @@ int checkboard (void) return 0; }
-phys_size_t -initdram(int board_type) -{
phys_size_t dram_size = 0;puts("Initializing....");-#ifdef CONFIG_SPD_EEPROM
dram_size = fsl_ddr_sdram();-#else
dram_size = fixed_sdram();-#endif
dram_size = setup_ddr_tlbs(dram_size / 0x100000);dram_size *= 0x100000;puts(" DDR: ");return dram_size;-}
#if !defined(CONFIG_SPD_EEPROM) /*
- Fixed sdram init -- doesn't use serial presence detect.
diff --git a/board/freescale/mpc8540ads/mpc8540ads.c b/board/freescale/mpc8540ads/mpc8540ads.c index d354a26..deab811 100644 --- a/board/freescale/mpc8540ads/mpc8540ads.c +++ b/board/freescale/mpc8540ads/mpc8540ads.c @@ -39,8 +39,6 @@ extern void ddr_enable_ecc(unsigned int dram_size); #endif
void local_bus_init(void); -void sdram_init(void); -long int fixed_sdram(void);
int checkboard (void) { @@ -61,54 +59,6 @@ int checkboard (void) return 0; }
-phys_size_t -initdram(int board_type) -{
long dram_size = 0;puts("Initializing\n");-#if defined(CONFIG_DDR_DLL)
{volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);uint temp_ddrdll = 0;/** Work around to stabilize DDR DLL*/temp_ddrdll = gur->ddrdllcr;gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;asm("sync;isync;msync");}-#endif
-#ifdef CONFIG_SPD_EEPROM
dram_size = fsl_ddr_sdram();dram_size = setup_ddr_tlbs(dram_size / 0x100000);dram_size *= 0x100000;-#else
dram_size = fixed_sdram();-#endif
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
/** Initialize and enable DDR ECC.*/ddr_enable_ecc(dram_size);-#endif
/** Initialize SDRAM.*/sdram_init();puts(" DDR: ");return dram_size;-}
/*
- Initialize Local Bus
*/ @@ -232,7 +182,7 @@ sdram_init(void) /*************************************************************************
- fixed sdram init -- doesn't use serial presence detect.
************************************************************************/ -long int fixed_sdram (void) +phys_size_t fixed_sdram(void) { #ifndef CONFIG_SYS_RAMBOOT volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); diff --git a/board/freescale/mpc8540ads/tlb.c b/board/freescale/mpc8540ads/tlb.c index a9925d5..adcc0ad 100644 --- a/board/freescale/mpc8540ads/tlb.c +++ b/board/freescale/mpc8540ads/tlb.c @@ -106,25 +106,6 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_BCSR, CONFIG_SYS_BCSR, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 7, BOOKE_PAGESZ_16K, 1),
-#if !defined(CONFIG_SPD_EEPROM)
/** TLB 8, 9: 128M DDR* 0x00000000 64M DDR System memory* 0x04000000 64M DDR System memory* Without SPD EEPROM configured DDR, this must be setup manually.* Make sure the TLB count at the top of this table is correct.* Likely it needs to be increased by two for these entries.*/-#error("Update the number of table entries in tlb1_entry")
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,MAS3_SX|MAS3_SW|MAS3_SR, 0,0, 8, BOOKE_PAGESZ_64M, 1),SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000,MAS3_SX|MAS3_SW|MAS3_SR, 0,0, 9, BOOKE_PAGESZ_64M, 1),-#endif };
int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/mpc8541cds/mpc8541cds.c b/board/freescale/mpc8541cds/mpc8541cds.c index 59ec604..59df2bd 100644 --- a/board/freescale/mpc8541cds/mpc8541cds.c +++ b/board/freescale/mpc8541cds/mpc8541cds.c @@ -42,7 +42,6 @@ extern void ddr_enable_ecc(unsigned int dram_size); #endif
void local_bus_init(void); -void sdram_init(void);
/*
- I/O Port configuration table
@@ -242,48 +241,6 @@ int checkboard (void) return 0; }
-phys_size_t -initdram(int board_type) -{
long dram_size = 0;puts("Initializing\n");-#if defined(CONFIG_DDR_DLL)
{/** Work around to stabilize DDR DLL MSYNC_IN.* Errata DDR9 seems to have been fixed.* This is now the workaround for Errata DDR11:* Override DLL = 1, Course Adj = 1, Tap Select = 0*/volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);gur->ddrdllcr = 0x81000000;asm("sync;isync;msync");udelay(200);}-#endif
dram_size = fsl_ddr_sdram();dram_size = setup_ddr_tlbs(dram_size / 0x100000);dram_size *= 0x100000;-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
/** Initialize and enable DDR ECC.*/ddr_enable_ecc(dram_size);-#endif
/** SDRAM Initialization*/sdram_init();puts(" DDR: ");return dram_size;-}
/*
- Initialize Local Bus
*/ diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c index 31c3fad..35d81db 100644 --- a/board/freescale/mpc8544ds/mpc8544ds.c +++ b/board/freescale/mpc8544ds/mpc8544ds.c @@ -67,23 +67,6 @@ int checkboard (void) return 0; }
-phys_size_t -initdram(int board_type) -{
long dram_size = 0;puts("Initializing\n");dram_size = fsl_ddr_sdram();dram_size = setup_ddr_tlbs(dram_size / 0x100000);dram_size *= 0x100000;puts(" DDR: ");return dram_size;-}
#ifdef CONFIG_PCI1 static struct pci_controller pci1_hose; #endif diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index 14c902c..230cbd1 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -41,7 +41,6 @@ DECLARE_GLOBAL_DATA_PTR;
void local_bus_init(void); -void sdram_init(void);
int checkboard (void) { @@ -74,43 +73,6 @@ int checkboard (void) return 0; }
-phys_size_t -initdram(int board_type) -{
long dram_size = 0;puts("Initializing\n");-#if defined(CONFIG_DDR_DLL)
{/** Work around to stabilize DDR DLL MSYNC_IN.* Errata DDR9 seems to have been fixed.* This is now the workaround for Errata DDR11:* Override DLL = 1, Course Adj = 1, Tap Select = 0*/volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);gur->ddrdllcr = 0x81000000;asm("sync;isync;msync");udelay(200);}-#endif
dram_size = fsl_ddr_sdram();dram_size = setup_ddr_tlbs(dram_size / 0x100000);dram_size *= 0x100000;/** SDRAM Initialization*/sdram_init();puts(" DDR: ");return dram_size;-}
/*
- Initialize Local Bus
*/ diff --git a/board/freescale/mpc8555cds/mpc8555cds.c b/board/freescale/mpc8555cds/mpc8555cds.c index edaba26..5fe7f13 100644 --- a/board/freescale/mpc8555cds/mpc8555cds.c +++ b/board/freescale/mpc8555cds/mpc8555cds.c @@ -40,7 +40,6 @@ extern void ddr_enable_ecc(unsigned int dram_size); #endif
void local_bus_init(void); -void sdram_init(void);
/*
- I/O Port configuration table
@@ -240,50 +239,6 @@ int checkboard (void) return 0; }
-phys_size_t -initdram(int board_type) -{
long dram_size = 0;puts("Initializing\n");-#if defined(CONFIG_DDR_DLL)
{/** Work around to stabilize DDR DLL MSYNC_IN.* Errata DDR9 seems to have been fixed.* This is now the workaround for Errata DDR11:* Override DLL = 1, Course Adj = 1, Tap Select = 0*/volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);gur->ddrdllcr = 0x81000000;asm("sync;isync;msync");udelay(200);}-#endif
dram_size = fsl_ddr_sdram();dram_size = setup_ddr_tlbs(dram_size / 0x100000);dram_size *= 0x100000;-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
/** Initialize and enable DDR ECC.*/ddr_enable_ecc(dram_size);-#endif
/** SDRAM Initialization*/sdram_init();puts(" DDR: ");return dram_size;-}
/*
- Initialize Local Bus
*/ diff --git a/board/freescale/mpc8560ads/mpc8560ads.c b/board/freescale/mpc8560ads/mpc8560ads.c index 1761431..38f59d1 100644 --- a/board/freescale/mpc8560ads/mpc8560ads.c +++ b/board/freescale/mpc8560ads/mpc8560ads.c @@ -44,8 +44,6 @@ extern void ddr_enable_ecc(unsigned int dram_size);
void local_bus_init(void); -void sdram_init(void); -long int fixed_sdram(void);
/* @@ -266,54 +264,6 @@ int checkboard (void) return 0; }
-phys_size_t -initdram(int board_type) -{
long dram_size = 0;puts("Initializing\n");-#if defined(CONFIG_DDR_DLL)
{volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);uint temp_ddrdll = 0;/** Work around to stabilize DDR DLL*/temp_ddrdll = gur->ddrdllcr;gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;asm("sync;isync;msync");}-#endif
-#ifdef CONFIG_SPD_EEPROM
dram_size = fsl_ddr_sdram();dram_size = setup_ddr_tlbs(dram_size / 0x100000);dram_size *= 0x100000;-#else
dram_size = fixed_sdram();-#endif
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
/** Initialize and enable DDR ECC.*/ddr_enable_ecc(dram_size);-#endif
/** Initialize SDRAM.*/sdram_init();puts(" DDR: ");return dram_size;-}
/*
- Initialize Local Bus
*/ @@ -437,7 +387,7 @@ sdram_init(void) /*************************************************************************
- fixed sdram init -- doesn't use serial presence detect.
************************************************************************/ -long int fixed_sdram (void) +phys_size_t fixed_sdram(void) { #ifndef CONFIG_SYS_RAMBOOT volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); diff --git a/board/freescale/mpc8560ads/tlb.c b/board/freescale/mpc8560ads/tlb.c index a9925d5..adcc0ad 100644 --- a/board/freescale/mpc8560ads/tlb.c +++ b/board/freescale/mpc8560ads/tlb.c @@ -106,25 +106,6 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_BCSR, CONFIG_SYS_BCSR, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 7, BOOKE_PAGESZ_16K, 1),
-#if !defined(CONFIG_SPD_EEPROM)
/** TLB 8, 9: 128M DDR* 0x00000000 64M DDR System memory* 0x04000000 64M DDR System memory* Without SPD EEPROM configured DDR, this must be setup manually.* Make sure the TLB count at the top of this table is correct.* Likely it needs to be increased by two for these entries.*/-#error("Update the number of table entries in tlb1_entry")
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,MAS3_SX|MAS3_SW|MAS3_SR, 0,0, 8, BOOKE_PAGESZ_64M, 1),SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000,MAS3_SX|MAS3_SW|MAS3_SR, 0,0, 9, BOOKE_PAGESZ_64M, 1),-#endif };
int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c index d74fcac..ee4c807 100644 --- a/board/freescale/mpc8568mds/mpc8568mds.c +++ b/board/freescale/mpc8568mds/mpc8568mds.c @@ -100,7 +100,6 @@ const qe_iop_conf_t qe_iop_conf_tab[] = { };
void local_bus_init(void); -void sdram_init(void);
int board_early_init_f (void) { @@ -137,43 +136,6 @@ int checkboard (void) return 0; }
-phys_size_t -initdram(int board_type) -{
long dram_size = 0;puts("Initializing\n");-#if defined(CONFIG_DDR_DLL)
{/** Work around to stabilize DDR DLL MSYNC_IN.* Errata DDR9 seems to have been fixed.* This is now the workaround for Errata DDR11:* Override DLL = 1, Course Adj = 1, Tap Select = 0*/volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);gur->ddrdllcr = 0x81000000;asm("sync;isync;msync");udelay(200);}-#endif
dram_size = fsl_ddr_sdram();dram_size = setup_ddr_tlbs(dram_size / 0x100000);dram_size *= 0x100000;/** SDRAM Initialization*/sdram_init();puts(" DDR: ");return dram_size;-}
/*
- Initialize Local Bus
*/ diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c index dc0884e..12a417c 100644 --- a/board/freescale/mpc8569mds/mpc8569mds.c +++ b/board/freescale/mpc8569mds/mpc8569mds.c @@ -44,8 +44,6 @@ #include "../common/pq-mds-pib.h" #endif
-phys_size_t fixed_sdram(void);
const qe_iop_conf_t qe_iop_conf_tab[] = { /* QE_MUX_MDC */ {2, 31, 1, 0, 1}, /* QE_MUX_MDC */ @@ -244,40 +242,6 @@ int checkboard (void) return 0; }
-phys_size_t -initdram(int board_type) -{
long dram_size = 0;puts("Initializing\n");-#if defined(CONFIG_DDR_DLL)
/** Work around to stabilize DDR DLL MSYNC_IN.* Errata DDR9 seems to have been fixed.* This is now the workaround for Errata DDR11:* Override DLL = 1, Course Adj = 1, Tap Select = 0*/volatile ccsr_gur_t *gur =(void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);out_be32(&gur->ddrdllcr, 0x81000000);udelay(200);-#endif
-#ifdef CONFIG_SPD_EEPROM
dram_size = fsl_ddr_sdram();-#else
dram_size = fixed_sdram();-#endif
dram_size = setup_ddr_tlbs(dram_size / 0x100000);dram_size *= 0x100000;puts(" DDR: ");return dram_size;-}
#if !defined(CONFIG_SPD_EEPROM) phys_size_t fixed_sdram(void) { diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c index 120f35c..796aacf 100644 --- a/board/freescale/mpc8572ds/mpc8572ds.c +++ b/board/freescale/mpc8572ds/mpc8572ds.c @@ -38,8 +38,6 @@
#include "../common/sgmii_riser.h"
-long int fixed_sdram(void);
int checkboard (void) { u8 vboot; @@ -73,23 +71,6 @@ int checkboard (void) return 0; }
-phys_size_t initdram(int board_type) -{
phys_size_t dram_size = 0;puts("Initializing....");-#ifdef CONFIG_SPD_EEPROM
dram_size = fsl_ddr_sdram();-#else
dram_size = fixed_sdram();-#endif
dram_size = setup_ddr_tlbs(dram_size / 0x100000);dram_size *= 0x100000;puts(" DDR: ");return dram_size;-}
#if !defined(CONFIG_SPD_EEPROM) /* diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c index 7cb549b..e3e8300 100644 --- a/board/freescale/p1022ds/p1022ds.c +++ b/board/freescale/p1022ds/p1022ds.c @@ -76,19 +76,6 @@ int checkboard(void) return 0; }
-phys_size_t initdram(int board_type) -{
phys_size_t dram_size = 0;puts("Initializing....\n");dram_size = fsl_ddr_sdram();dram_size = setup_ddr_tlbs(dram_size / 0x100000) * 0x100000;puts(" DDR: ");return dram_size;-}
#define CONFIG_TFP410_I2C_ADDR 0x38
/* Masks for the SSI_TDM and AUDCLK bits of the ngPIXIS BRDCFG1 register. */ diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c index 15b46b0..e54fde2 100644 --- a/board/freescale/p1_p2_rdb/ddr.c +++ b/board/freescale/p1_p2_rdb/ddr.c @@ -239,19 +239,6 @@ phys_size_t fixed_sdram (void)
fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
set_ddr_laws(0, ddr_size, LAW_TRGT_IF_DDR_1); return ddr_size;}
-phys_size_t initdram(int board_type) -{
phys_size_t dram_size = 0;dram_size = fixed_sdram();set_ddr_laws(0, dram_size, LAW_TRGT_IF_DDR_1);dram_size = setup_ddr_tlbs(dram_size / 0x100000);dram_size *= 0x100000;puts("DDR: ");return dram_size;-} diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c index b05ef98..7ad8544 100644 --- a/board/freescale/p2020ds/p2020ds.c +++ b/board/freescale/p2020ds/p2020ds.c @@ -43,8 +43,6 @@
DECLARE_GLOBAL_DATA_PTR;
-phys_size_t fixed_sdram(void);
int checkboard(void) { u8 sw; @@ -69,31 +67,6 @@ int checkboard(void) return 0; }
-phys_size_t initdram(int board_type) -{
phys_size_t dram_size = 0;puts("Initializing....");-#ifdef CONFIG_DDR_SPD
dram_size = fsl_ddr_sdram();-#else
dram_size = fixed_sdram();if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,dram_size,LAW_TRGT_IF_DDR) < 0) {printf("ERROR setting Local Access Windows for DDR\n");return 0;};-#endif
dram_size = setup_ddr_tlbs(dram_size / 0x100000);dram_size *= 0x100000;puts(" DDR: ");return dram_size;-}
#if !defined(CONFIG_DDR_SPD) /*
- Fixed sdram init -- doesn't use serial presence detect.
@@ -169,6 +142,13 @@ phys_size_t fixed_sdram(void) udelay(500); #endif
if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,CONFIG_SYS_SDRAM_SIZE * 1024 * 1024,LAW_TRGT_IF_DDR) < 0) {printf("ERROR setting Local Access Windows for DDR\n");return 0;};return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;}
diff --git a/board/mpc8540eval/mpc8540eval.c b/board/mpc8540eval/mpc8540eval.c index f1ab360..63a0035 100644 --- a/board/mpc8540eval/mpc8540eval.c +++ b/board/mpc8540eval/mpc8540eval.c @@ -31,8 +31,6 @@ #include <asm/fsl_ddr_sdram.h> #include <spd_sdram.h>
-long int fixed_sdram (void);
int board_pre_init (void) { #if defined(CONFIG_PCI) @@ -108,54 +106,6 @@ void sdram_init(void) #endif }
-phys_size_t initdram(int board_type) -{
long dram_size = 0;-#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);-#endif
-#if defined(CONFIG_DDR_DLL)
uint temp_ddrdll = 0;/* Work around to stabilize DDR DLL */temp_ddrdll = gur->ddrdllcr;gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;asm("sync;isync;msync");-#endif
-#if defined(CONFIG_SPD_EEPROM)
dram_size = fsl_ddr_sdram();dram_size = setup_ddr_tlbs(dram_size / 0x100000);dram_size *= 0x100000;-#else
dram_size = fixed_sdram();-#endif
-#if defined(CONFIG_SYS_RAMBOOT)
return dram_size;-#endif
sdram_init();-#if defined(CONFIG_DDR_ECC)
{/* Initialize all of memory for ECC, then* enable errors */volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size);/* Enable errors for ECC */ddr->err_disable = 0x00000000;asm("sync;isync;msync");}-#endif
return dram_size;-}
#if defined(CONFIG_SYS_DRAM_TEST) int testdram (void) { @@ -194,7 +144,7 @@ int testdram (void) /*************************************************************************
- fixed sdram init -- doesn't use serial presence detect.
************************************************************************/ -long int fixed_sdram (void) +phys_size_t fixed_sdram(void) { #ifndef CONFIG_SYS_RAMBOOT volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); diff --git a/board/pm854/pm854.c b/board/pm854/pm854.c index 0b8ea81..bbaf4fd 100644 --- a/board/pm854/pm854.c +++ b/board/pm854/pm854.c @@ -34,14 +34,7 @@ #include <asm/fsl_ddr_sdram.h> #include <spd_sdram.h>
-#if defined(CONFIG_DDR_ECC) -extern void ddr_enable_ecc(unsigned int dram_size); -#endif
void local_bus_init(void); -void sdram_init(void); -long int fixed_sdram(void);
int board_early_init_f (void) { @@ -73,59 +66,6 @@ int checkboard (void) return 0; }
-phys_size_t -initdram(int board_type) -{
long dram_size = 0;puts("Initializing\n");-#if defined(CONFIG_DDR_DLL)
{volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);int i,x;x = 10;/** Work around to stabilize DDR DLL*/gur->ddrdllcr = 0x81000000;asm("sync;isync;msync");udelay (200);while (gur->ddrdllcr != 0x81000100){gur->devdisr = gur->devdisr | 0x00010000;asm("sync;isync;msync");for (i=0; i<x; i++);gur->devdisr = gur->devdisr & 0xfff7ffff;asm("sync;isync;msync");x++;}}-#endif
-#if defined(CONFIG_SPD_EEPROM)
dram_size = fsl_ddr_sdram();dram_size = setup_ddr_tlbs(dram_size / 0x100000);dram_size *= 0x100000;-#else
dram_size = fixed_sdram ();-#endif
-#if defined(CONFIG_DDR_ECC)
/** Initialize and enable DDR ECC.*/ddr_enable_ecc(dram_size);-#endif
puts(" DDR: ");return dram_size;-}
/*
- Initialize Local Bus
*/ @@ -225,7 +165,7 @@ int testdram (void) /*************************************************************************
- fixed sdram init -- doesn't use serial presence detect.
************************************************************************/ -long int fixed_sdram (void) +phys_size_t fixed_sdram(void) { #ifndef CONFIG_SYS_RAMBOOT volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); diff --git a/board/pm854/tlb.c b/board/pm854/tlb.c index dadb75c..482eb38 100644 --- a/board/pm854/tlb.c +++ b/board/pm854/tlb.c @@ -98,20 +98,6 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_LBC_BASE, CONFIG_SYS_LBC_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 6, BOOKE_PAGESZ_64M, 1),
-#if !defined(CONFIG_SPD_EEPROM)
/** TLB 7: 256M DDR* 0x00000000 256M DDR System memory* Without SPD EEPROM configured DDR, this must be setup manually.* Make sure the TLB count at the top of this table is correct.* Likely it needs to be increased by two for these entries.*/SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,MAS3_SX|MAS3_SW|MAS3_SR, 0,0, 7, BOOKE_PAGESZ_256M, 1),-#endif };
int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/pm856/pm856.c b/board/pm856/pm856.c index 4e059b0..3791216 100644 --- a/board/pm856/pm856.c +++ b/board/pm856/pm856.c @@ -41,7 +41,6 @@ extern void ddr_enable_ecc(unsigned int dram_size); #endif
void local_bus_init(void); -long int fixed_sdram(void);
/*
- I/O Port configuration table
@@ -228,60 +227,6 @@ int checkboard (void) }
-phys_size_t -initdram(int board_type) -{
long dram_size = 0;puts("Initializing\n");-#if defined(CONFIG_DDR_DLL)
{volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);int i,x;x = 10;/** Work around to stabilize DDR DLL*/gur->ddrdllcr = 0x81000000;asm("sync;isync;msync");udelay (200);while (gur->ddrdllcr != 0x81000100){gur->devdisr = gur->devdisr | 0x00010000;asm("sync;isync;msync");for (i=0; i<x; i++);gur->devdisr = gur->devdisr & 0xfff7ffff;asm("sync;isync;msync");x++;}}-#endif
-#if defined(CONFIG_SPD_EEPROM)
dram_size = fsl_ddr_sdram();dram_size = setup_ddr_tlbs(dram_size / 0x100000);dram_size *= 0x100000;-#else
dram_size = fixed_sdram ();-#endif
-#if defined(CONFIG_DDR_ECC)
/** Initialize and enable DDR ECC.*/ddr_enable_ecc(dram_size);-#endif
puts(" DDR: ");return dram_size;-}
/*
- Initialize Local Bus
*/ @@ -380,7 +325,7 @@ int testdram (void) /*************************************************************************
- fixed sdram init -- doesn't use serial presence detect.
************************************************************************/ -long int fixed_sdram (void) +phys_size_t fixed_sdram(void) { #ifndef CONFIG_SYS_RAMBOOT volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); diff --git a/board/pm856/tlb.c b/board/pm856/tlb.c index dadb75c..482eb38 100644 --- a/board/pm856/tlb.c +++ b/board/pm856/tlb.c @@ -98,20 +98,6 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_LBC_BASE, CONFIG_SYS_LBC_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 6, BOOKE_PAGESZ_64M, 1),
-#if !defined(CONFIG_SPD_EEPROM)
/** TLB 7: 256M DDR* 0x00000000 256M DDR System memory* Without SPD EEPROM configured DDR, this must be setup manually.* Make sure the TLB count at the top of this table is correct.* Likely it needs to be increased by two for these entries.*/SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,MAS3_SX|MAS3_SW|MAS3_SR, 0,0, 7, BOOKE_PAGESZ_256M, 1),-#endif };
int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index 272428f..2d24890 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -42,8 +42,6 @@ DECLARE_GLOBAL_DATA_PTR;
void local_bus_init(void); -void sdram_init(void); -long int fixed_sdram (void);
int board_early_init_f (void) { @@ -68,47 +66,6 @@ int checkboard (void) return 0; }
-phys_size_t -initdram(int board_type) -{
long dram_size = 0;puts("Initializing\n");-#if defined(CONFIG_DDR_DLL)
{/** Work around to stabilize DDR DLL MSYNC_IN.* Errata DDR9 seems to have been fixed.* This is now the workaround for Errata DDR11:* Override DLL = 1, Course Adj = 1, Tap Select = 0*/volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);out_be32(&gur->ddrdllcr, 0x81000000);asm("sync;isync;msync");udelay(200);}-#endif
-#if defined(CONFIG_SPD_EEPROM)
dram_size = fsl_ddr_sdram();dram_size = setup_ddr_tlbs(dram_size / 0x100000);dram_size *= 0x100000;-#else
dram_size = fixed_sdram ();-#endif
/** SDRAM Initialization*/sdram_init();puts(" DDR: ");return dram_size;-}
/*
- Initialize Local Bus
*/ @@ -267,7 +224,7 @@ testdram(void)
- fixed_sdram init -- doesn't use serial presence detect.
- assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed.
************************************************************************/ -long int fixed_sdram (void) +phys_size_t fixed_sdram(void) { volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c index 38bdeb3..bb4c052 100644 --- a/board/sbc8548/tlb.c +++ b/board/sbc8548/tlb.c @@ -65,44 +65,34 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 1, BOOKE_PAGESZ_1G, 1),
/*
* TLB 2: 256M Cacheable, non-guarded* 0x0 256M DDR SDRAM*/-#if !defined(CONFIG_SPD_EEPROM)
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,MAS3_SX|MAS3_SW|MAS3_SR, 0,0, 2, BOOKE_PAGESZ_256M, 1),-#endif
/** TLB 3: 64M Non-cacheable, guarded
* TLB 2: 64M Non-cacheable, guarded * 0xe0000000 1M CCSRBAR * 0xe2000000 8M PCI1 IO * 0xe2800000 8M PCIe IO */ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_64M, 1),
0, 2, BOOKE_PAGESZ_64M, 1), /*
* TLB 4: 64M Cacheable, non-guarded
* TLB 3: 64M Cacheable, non-guarded * 0xf0000000 64M LBC SDRAM First half */ SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 4, BOOKE_PAGESZ_64M, 1),
0, 3, BOOKE_PAGESZ_64M, 1), /*
* TLB 5: 64M Cacheable, non-guarded
* TLB 4: 64M Cacheable, non-guarded * 0xf4000000 64M LBC SDRAM Second half */ SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000, CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000, MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 5, BOOKE_PAGESZ_64M, 1),
0, 4, BOOKE_PAGESZ_64M, 1), /*
* TLB 6: 16M Cacheable, non-guarded
* TLB 5: 16M Cacheable, non-guarded * 0xf8000000 1M 7-segment LED display * 0xf8100000 1M User switches * 0xf8300000 1M Board revision@@ -110,24 +100,24 @@ struct fsl_e_tlb_entry tlb_table[] = { */ SET_TLB_ENTRY(1, CONFIG_SYS_EPLD_BASE, CONFIG_SYS_EPLD_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_16M, 1),
0, 5, BOOKE_PAGESZ_16M, 1), /*
* TLB 7: 4M Non-cacheable, guarded
* TLB 6: 4M Non-cacheable, guarded * 0xfb800000 4M 1st 4MB block of 64MB user FLASH */ SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 7, BOOKE_PAGESZ_4M, 1),
0, 6, BOOKE_PAGESZ_4M, 1), /*
* TLB 8: 4M Non-cacheable, guarded
* TLB 7: 4M Non-cacheable, guarded * 0xfbc00000 4M 2nd 4MB block of 64MB user FLASH */ SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x400000, CONFIG_SYS_ALT_FLASH + 0x400000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 8, BOOKE_PAGESZ_4M, 1),
0, 7, BOOKE_PAGESZ_4M, 1),};
diff --git a/board/sbc8560/sbc8560.c b/board/sbc8560/sbc8560.c index 77abde5..53278d3 100644 --- a/board/sbc8560/sbc8560.c +++ b/board/sbc8560/sbc8560.c @@ -38,8 +38,6 @@ #include <libfdt.h> #include <fdt_support.h>
-long int fixed_sdram (void);
/*
- I/O Port configuration table
@@ -263,95 +261,6 @@ int checkboard (void) }
-phys_size_t initdram (int board_type) -{
long dram_size = 0;-#if 0 -#if !defined(CONFIG_RAM_AS_FLASH)
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;sys_info_t sysinfo;uint temp_lbcdll = 0;-#endif -#endif /* 0 */ -#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);-#endif -#if defined(CONFIG_DDR_DLL)
uint temp_ddrdll = 0;/* Work around to stabilize DDR DLL */temp_ddrdll = gur->ddrdllcr;gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;asm("sync;isync;msync");-#endif
-#if defined(CONFIG_SPD_EEPROM)
dram_size = fsl_ddr_sdram();dram_size = setup_ddr_tlbs(dram_size / 0x100000);dram_size *= 0x100000;-#else
dram_size = fixed_sdram ();-#endif
-#if 0 -#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus SDRAM is not emulating flash */
get_sys_info(&sysinfo);/* if localbus freq is less than 66MHz,we use bypass mode,otherwise use DLL */if(sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & 0x0f) < 66000000) {lbc->lcrr = (CONFIG_SYS_LBC_LCRR & 0x0fffffff)| 0x80000000;} else {-#if defined(CONFIG_MPC85xx_REV1) /* need change CLKDIV before enable DLL */
lbc->lcrr = 0x10000004; /* default CLKDIV is 8, change it to 4 temporarily */-#endif
lbc->lcrr = CONFIG_SYS_LBC_LCRR & 0x7fffffff;udelay(200);temp_lbcdll = gur->lbcdllcr;gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;asm("sync;isync;msync");}set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); /* 64MB SDRAM */set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);lbc->lbcr = CONFIG_SYS_LBC_LBCR;lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;asm("sync");(unsigned int) * (ulong *)0 = 0x000000ff;lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;asm("sync");(unsigned int) * (ulong *)0 = 0x000000ff;lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3;asm("sync");(unsigned int) * (ulong *)0 = 0x000000ff;lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;asm("sync");(unsigned int) * (ulong *)0 = 0x000000ff;lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5;asm("sync");lbc->lsrt = CONFIG_SYS_LBC_LSRT;asm("sync");lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;asm("sync");-#endif -#endif
-#if defined(CONFIG_DDR_ECC)
{/* Initialize all of memory for ECC, then* enable errors */volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size);/* Enable errors for ECC */ddr->err_disable = 0x00000000;asm("sync;isync;msync");}-#endif
return dram_size;-}
#if defined(CONFIG_SYS_DRAM_TEST) int testdram (void) { @@ -390,7 +299,7 @@ int testdram (void) /*************************************************************************
- fixed sdram init -- doesn't use serial presence detect.
************************************************************************/ -long int fixed_sdram (void) +phys_size_t fixed_sdram(void) {
#define CONFIG_SYS_DDR_CONTROL 0xc2000000 diff --git a/board/socrates/sdram.c b/board/socrates/sdram.c index ef897b2..c8235f4 100644 --- a/board/socrates/sdram.c +++ b/board/socrates/sdram.c @@ -39,7 +39,7 @@
so this should be extended for other future boardsusing this routine!*/ -long int fixed_sdram(void) +phys_size_t fixed_sdram(void) { volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
@@ -77,19 +77,6 @@ long int fixed_sdram(void) } #endif
-phys_size_t initdram (int board_type) -{
long dram_size = 0;-#if defined(CONFIG_SPD_EEPROM)
dram_size = fsl_ddr_sdram();dram_size = setup_ddr_tlbs(dram_size / 0x100000);dram_size *= 0x100000;-#else
dram_size = fixed_sdram();-#endif
return dram_size;-}
#if defined(CONFIG_SYS_DRAM_TEST) int testdram (void) { diff --git a/board/stx/stxgp3/stxgp3.c b/board/stx/stxgp3/stxgp3.c index 25d5211..63068a5 100644 --- a/board/stx/stxgp3/stxgp3.c +++ b/board/stx/stxgp3/stxgp3.c @@ -40,8 +40,6 @@ #include <spd_sdram.h> #include <miiphy.h>
-long int fixed_sdram (void);
/*
- I/O Port configuration table
@@ -277,36 +275,6 @@ show_activity(int flag) next_led_update += (get_tbclk() / 4); }
-phys_size_t -initdram (int board_type) -{
long dram_size = 0;-#if defined(CONFIG_DDR_DLL)
{volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);uint temp_ddrdll = 0;/* Work around to stabilize DDR DLL */temp_ddrdll = gur->ddrdllcr;gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;asm("sync;isync;msync");}-#endif
dram_size = fsl_ddr_sdram();dram_size = setup_ddr_tlbs(dram_size / 0x100000);dram_size *= 0x100000;-#if defined(CONFIG_DDR_ECC)
/* Initialize and enable DDR ECC.*/ddr_enable_ecc(dram_size);-#endif
return dram_size;-}
#if defined(CONFIG_SYS_DRAM_TEST) int testdram (void) diff --git a/board/stx/stxssa/stxssa.c b/board/stx/stxssa/stxssa.c index 1e0acab..a630cc8 100644 --- a/board/stx/stxssa/stxssa.c +++ b/board/stx/stxssa/stxssa.c @@ -41,8 +41,6 @@ #include <miiphy.h> #include <netdev.h>
-long int fixed_sdram (void);
/*
- I/O Port configuration table
@@ -294,37 +292,6 @@ show_activity(int flag) next_led_update += (get_tbclk() / 4); }
-phys_size_t -initdram (int board_type) -{
long dram_size = 0;-#if defined(CONFIG_DDR_DLL)
{volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);uint temp_ddrdll = 0;/* Work around to stabilize DDR DLL */temp_ddrdll = gur->ddrdllcr;gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;asm("sync;isync;msync");}-#endif
dram_size = fsl_ddr_sdram();dram_size = setup_ddr_tlbs(dram_size / 0x100000);dram_size *= 0x100000;-#if defined(CONFIG_DDR_ECC)
/* Initialize and enable DDR ECC.*/ddr_enable_ecc(dram_size);-#endif
return dram_size;-}
#if defined(CONFIG_SYS_DRAM_TEST) int testdram (void) { diff --git a/board/tqc/tqm85xx/sdram.c b/board/tqc/tqm85xx/sdram.c index 260cd1c..b2d3185 100644 --- a/board/tqc/tqm85xx/sdram.c +++ b/board/tqc/tqm85xx/sdram.c @@ -394,43 +394,6 @@ static phys_size_t sdram_setup(int casl) return (i < N_DDR_CS_CONF) ? ddr_cs_conf[i].size : 0; }
-phys_size_t initdram (int board_type) -{
phys_size_t dram_size = 0;-#if defined(CONFIG_DDR_DLL)
/** This DLL-Override only used on TQM8540 and TQM8560*/{volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);int i, x;x = 10;/** Work around to stabilize DDR DLL*/gur->ddrdllcr = 0x81000000;asm ("sync; isync; msync");udelay (200);while (gur->ddrdllcr != 0x81000100) {gur->devdisr = gur->devdisr | 0x00010000;asm ("sync; isync; msync");for (i = 0; i < x; i++);gur->devdisr = gur->devdisr & 0xfff7ffff;asm ("sync; isync; msync");x++;}}-#endif
dram_size = fixed_sdram();return dram_size;-}
#if defined(CONFIG_SYS_DRAM_TEST) int testdram (void) { diff --git a/board/tqc/tqm85xx/tlb.c b/board/tqc/tqm85xx/tlb.c index 75dd348..f9f8cc9 100644 --- a/board/tqc/tqm85xx/tlb.c +++ b/board/tqc/tqm85xx/tlb.c @@ -120,36 +120,6 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY (1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 6, BOOKE_PAGESZ_64M, 1),
-#if defined(CONFIG_TQM8548_AG) || defined (CONFIG_TQM8548_BE)
/** TLB 7+8: 2G DDR, cache enabled* 0x00000000 2G DDR System memory* Without SPD EEPROM configured DDR, this must be setup manually.*/SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,MAS3_SX | MAS3_SW | MAS3_SR, 0,0, 7, BOOKE_PAGESZ_1G, 1),SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,MAS3_SX | MAS3_SW | MAS3_SR, 0,0, 8, BOOKE_PAGESZ_1G, 1),-#else
/** TLB 7+8: 512M DDR, cache disabled (needed for memory test)* 0x00000000 512M DDR System memory* Without SPD EEPROM configured DDR, this must be setup manually.*/SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,0, 7, BOOKE_PAGESZ_256M, 1),SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,0, 8, BOOKE_PAGESZ_256M, 1),-#endif #ifdef CONFIG_PCIE1 /* * TLB 9: 16M Non-cacheable, guarded @@ -228,23 +198,6 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY (1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 7, BOOKE_PAGESZ_64M, 1),
/** TLB 8+9: 512M DDR, cache disabled (needed for memory test)* 0x00000000 512M DDR System memory* Without SPD EEPROM configured DDR, this must be setup manually.* Make sure the TLB count at the top of this table is correct.* Likely it needs to be increased by two for these entries.*/SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,0, 8, BOOKE_PAGESZ_256M, 1),SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,0, 9, BOOKE_PAGESZ_256M, 1),#ifdef CONFIG_PCIE1 /* * TLB 10: 16M Non-cacheable, guarded diff --git a/board/xes/common/Makefile b/board/xes/common/Makefile index 7604f62..39d105f 100644 --- a/board/xes/common/Makefile +++ b/board/xes/common/Makefile @@ -33,8 +33,6 @@ COBJS-$(CONFIG_FSL_PCI_INIT) += fsl_8xxx_pci.o COBJS-$(CONFIG_MPC8572) += fsl_8xxx_clk.o COBJS-$(CONFIG_MPC86xx) += fsl_8xxx_clk.o COBJS-$(CONFIG_P2020) += fsl_8xxx_clk.o -COBJS-$(CONFIG_FSL_DDR2) += fsl_8xxx_ddr.o -COBJS-$(CONFIG_FSL_DDR3) += fsl_8xxx_ddr.o COBJS-$(CONFIG_MPC85xx) += fsl_8xxx_misc.o board.o COBJS-$(CONFIG_MPC86xx) += fsl_8xxx_misc.o board.o COBJS-$(CONFIG_NAND_ACTL) += actl_nand.o diff --git a/board/xes/common/fsl_8xxx_ddr.c b/board/xes/common/fsl_8xxx_ddr.c deleted file mode 100644 index 81ee70d..0000000 --- a/board/xes/common/fsl_8xxx_ddr.c +++ /dev/null @@ -1,46 +0,0 @@ -/*
- Copyright 2008 Extreme Engineering Solutions, Inc.
- See file CREDITS for list of people who contributed to this
- project.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- MA 02111-1307 USA
- */
-#include <common.h> -#include <asm/fsl_ddr_sdram.h> -#include <asm/mmu.h>
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) -extern void ddr_enable_ecc(unsigned int dram_size); -#endif
-phys_size_t initdram(int board_type) -{
phys_size_t dram_size = fsl_ddr_sdram();-#ifdef CONFIG_MPC85xx
dram_size = setup_ddr_tlbs(dram_size / 0x100000);dram_size *= 0x100000;-#endif
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
/* Initialize and enable DDR ECC */ddr_enable_ecc(dram_size);-#endif
return dram_size;-} diff --git a/board/xes/xpedite517x/xpedite517x.c b/board/xes/xpedite517x/xpedite517x.c index 0f7fa6c..572a908 100644 --- a/board/xes/xpedite517x/xpedite517x.c +++ b/board/xes/xpedite517x/xpedite517x.c @@ -22,6 +22,7 @@
#include <common.h> #include <asm/processor.h> +#include <asm/fsl_ddr_sdram.h> #include <asm/mmu.h> #include <asm/io.h> #include <fdt_support.h> @@ -71,6 +72,18 @@ int board_early_init_r(void) return 0; }
+phys_size_t initdram(int board_type) +{
phys_size_t dram_size = fsl_ddr_sdram();+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
/* Initialize and enable DDR ECC */ddr_enable_ecc(dram_size);+#endif
return dram_size;+}
#if defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup(void *blob, bd_t *bd) { diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index 890d6d9..d8f43d7 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -147,6 +147,10 @@
- DDR Setup
*/ #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#if defined(CONFIG_TQM_BIGFLASH) || \
(!defined(CONFIG_TQM8548_AG) && !defined(CONFIG_TQM8548_BE))+#define CONFIG_DDR_TLB_WIMGE (MAS2_I | MAS2_G) +#endif #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #ifdef CONFIG_TQM8548_AG
#define CONFIG_VERY_BIG_RAM
1.5.6.5
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