Re: [PATCH 2/2] riscv: cache: support cache enable in SPL stage

On Thu, Dec 14, 2023 at 02:09:37PM +0000, Zong Li wrote:

The power gating feature of pl2 should be enabled as early as possible, it would be better to put it in SPL stage.

Signed-off-by: Zong Li zong.li@sifive.com

arch/riscv/lib/sifive_cache.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+)

Reviewed-by: Leo Yu-Chi Liang ycliang@andestech.com