We planned to fetch peripheral rate through one generic API per peripheral. These generic peripheral functions are in turn expected to fetch apt values from a function refactored as per SoC versions. This patch adds suuport for fetching peripheral rates for Exynos5420 and Exynos5800.
Signed-off-by: Akshay Saraswat akshay.s@samsung.com --- arch/arm/cpu/armv7/exynos/clock.c | 211 +++++++++++++++++++++++++++------ arch/arm/include/asm/arch-exynos/clk.h | 8 ++ 2 files changed, 183 insertions(+), 36 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 863974a..9ac4579 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -27,7 +27,7 @@ struct clk_bit_info { };
/* periph_id src_bit div_bit prediv_bit */ -static struct clk_bit_info clk_bit_info[] = { +static struct clk_bit_info exynos5_bit_info[] = { {PERIPH_ID_UART0, 0, 0, -1}, {PERIPH_ID_UART1, 4, 4, -1}, {PERIPH_ID_UART2, 8, 8, -1}, @@ -65,6 +65,44 @@ static struct clk_bit_info clk_bit_info[] = { {PERIPH_ID_NONE, -1, -1, -1}, };
+static struct clk_bit_info exynos542x_bit_info[] = { + {PERIPH_ID_UART0, 4, 8, -1}, + {PERIPH_ID_UART1, 8, 12, -1}, + {PERIPH_ID_UART2, 12, 16, -1}, + {PERIPH_ID_UART3, 16, 20, -1}, + {PERIPH_ID_I2C0, -1, 8, -1}, + {PERIPH_ID_I2C1, -1, 8, -1}, + {PERIPH_ID_I2C2, -1, 8, -1}, + {PERIPH_ID_I2C3, -1, 8, -1}, + {PERIPH_ID_I2C4, -1, 8, -1}, + {PERIPH_ID_I2C5, -1, 8, -1}, + {PERIPH_ID_I2C6, -1, 8, -1}, + {PERIPH_ID_I2C7, -1, 8, -1}, + {PERIPH_ID_SPI0, 20, 20, 8}, + {PERIPH_ID_SPI1, 24, 24, 16}, + {PERIPH_ID_SPI2, 28, 28, 24}, + {PERIPH_ID_SDMMC0, 0, 0, -1}, + {PERIPH_ID_SDMMC1, 4, 10, -1}, + {PERIPH_ID_SDMMC2, 8, 20, -1}, + {PERIPH_ID_SDMMC3, -1, -1, -1}, + {PERIPH_ID_I2C8, -1, 8, -1}, + {PERIPH_ID_I2C9, -1, 8, -1}, + {PERIPH_ID_I2S0, 0, 0, 4}, + {PERIPH_ID_I2S1, 4, 12, 16}, + {PERIPH_ID_SROMC, -1, -1, -1}, + {PERIPH_ID_SPI3, 12, 16, 0}, + {PERIPH_ID_SPI4, 16, 20, 8}, + {PERIPH_ID_SDMMC4, 16, 0, 8}, + {PERIPH_ID_PWM0, 24, 28, -1}, + {PERIPH_ID_PWM1, 24, 28, -1}, + {PERIPH_ID_PWM2, 24, 28, -1}, + {PERIPH_ID_PWM3, 24, 28, -1}, + {PERIPH_ID_PWM4, 24, 28, -1}, + {PERIPH_ID_I2C10, -1, 8, -1}, + + {PERIPH_ID_NONE, -1, -1, -1}, +}; + /* Epll Clock division values to achive different frequency output */ static struct set_epll_con_val exynos5_epll_div[] = { { 192000000, 0, 48, 3, 1, 0 }, @@ -267,16 +305,62 @@ static unsigned long exynos5_get_pll_clk(int pllreg) return fout; }
+/* exynos5420: return pll clock frequency */ +static unsigned long exynos5420_get_pll_clk(int pllreg) +{ + struct exynos5420_clock *clk = + (struct exynos5420_clock *)samsung_get_base_clock(); + unsigned long r, k = 0; + + switch (pllreg) { + case APLL: + r = readl(&clk->apll_con0); + break; + case MPLL: + r = readl(&clk->mpll_con0); + break; + case EPLL: + r = readl(&clk->epll_con0); + k = readl(&clk->epll_con1); + break; + case VPLL: + r = readl(&clk->vpll_con0); + k = readl(&clk->vpll_con1); + break; + case BPLL: + r = readl(&clk->bpll_con0); + break; + case RPLL: + r = readl(&clk->rpll_con0); + k = readl(&clk->rpll_con1); + break; + case SPLL: + r = readl(&clk->spll_con0); + break; + default: + printf("Unsupported PLL (%d)\n", pllreg); + return 0; + } + + return exynos_get_pll_clk(pllreg, r, k); +} + static struct clk_bit_info *get_clk_bit_info(int peripheral) { int i; + struct clk_bit_info *info; + + if (proid_is_exynos5420() || proid_is_exynos5800()) + info = exynos542x_bit_info; + else + info = exynos5_bit_info;
- for (i = 0; exynos5_bit_info[i].id != PERIPH_ID_NONE; i++) { - if (exynos5_bit_info[i].id == peripheral) + for (i = 0; info[i].id != PERIPH_ID_NONE; i++) { + if (info[i].id == peripheral) break; }
- return &exynos5_bit_info[i]; + return &info[i]; }
static unsigned long exynos5_get_periph_rate(int peripheral) @@ -375,52 +459,107 @@ static unsigned long exynos5_get_periph_rate(int peripheral) return sub_clk; }
-unsigned long clock_get_periph_rate(int peripheral) -{ - if (cpu_is_exynos5()) - return exynos5_get_periph_rate(peripheral); - else - return 0; -} - -/* exynos5420: return pll clock frequency */ -static unsigned long exynos5420_get_pll_clk(int pllreg) +static unsigned long exynos542x_get_periph_rate(int peripheral) { + struct clk_bit_info *bit_info = get_clk_bit_info(peripheral); + unsigned long sclk, sub_clk; + unsigned int src, div, sub_div = 0; struct exynos5420_clock *clk = - (struct exynos5420_clock *)samsung_get_base_clock(); - unsigned long r, k = 0; + (struct exynos5420_clock *)samsung_get_base_clock();
- switch (pllreg) { - case APLL: - r = readl(&clk->apll_con0); + switch (peripheral) { + case PERIPH_ID_UART0: + case PERIPH_ID_UART1: + case PERIPH_ID_UART2: + case PERIPH_ID_UART3: + src = readl(&clk->src_peric0); + div = readl(&clk->div_peric0); break; - case MPLL: - r = readl(&clk->mpll_con0); + case PERIPH_ID_PWM0: + case PERIPH_ID_PWM1: + case PERIPH_ID_PWM2: + case PERIPH_ID_PWM3: + case PERIPH_ID_PWM4: + src = readl(&clk->src_peric0); + div = readl(&clk->div_peric0); break; - case EPLL: - r = readl(&clk->epll_con0); - k = readl(&clk->epll_con1); + case PERIPH_ID_SPI0: + case PERIPH_ID_SPI1: + case PERIPH_ID_SPI2: + src = readl(&clk->src_peric1); + div = readl(&clk->div_peric1); + sub_div = readl(&clk->div_peric4); break; - case VPLL: - r = readl(&clk->vpll_con0); - k = readl(&clk->vpll_con1); + case PERIPH_ID_SPI3: + case PERIPH_ID_SPI4: + src = readl(&clk->src_isp); + div = readl(&clk->div_isp1); + sub_div = readl(&clk->div_isp1); break; - case BPLL: - r = readl(&clk->bpll_con0); + case PERIPH_ID_SDMMC0: + case PERIPH_ID_SDMMC1: + case PERIPH_ID_SDMMC2: + case PERIPH_ID_SDMMC3: + src = readl(&clk->src_fsys); + div = readl(&clk->div_fsys1); break; - case RPLL: - r = readl(&clk->rpll_con0); - k = readl(&clk->rpll_con1); + case PERIPH_ID_I2C0: + case PERIPH_ID_I2C1: + case PERIPH_ID_I2C2: + case PERIPH_ID_I2C3: + case PERIPH_ID_I2C4: + case PERIPH_ID_I2C5: + case PERIPH_ID_I2C6: + case PERIPH_ID_I2C7: + case PERIPH_ID_I2C8: + case PERIPH_ID_I2C9: + case PERIPH_ID_I2C10: + sclk = exynos5420_get_pll_clk(MPLL); + sub_div = ((readl(&clk->div_top1) >> bit_info->div_bit) + & 0x7) + 1; + return sclk / sub_div; + default: + debug("%s: invalid peripheral %d", __func__, peripheral); + return -1; + }; + + src = (src >> bit_info->src_bit) & 0xf; + + switch (src) { + case EXYNOS_SRC_MPLL: + sclk = exynos5420_get_pll_clk(MPLL); break; - case SPLL: - r = readl(&clk->spll_con0); + case EXYNOS_SRC_EPLL: + sclk = exynos5420_get_pll_clk(EPLL); + break; + case EXYNOS_SRC_RPLL: + sclk = exynos5420_get_pll_clk(RPLL); break; default: - printf("Unsupported PLL (%d)\n", pllreg); return 0; }
- return exynos_get_pll_clk(pllreg, r, k); + /* Ratio clock division for this peripheral */ + div = (div >> bit_info->div_bit) & 0xf; + sub_clk = sclk / (div + 1); + + if (bit_info->prediv_bit >= 0) { + sub_div = (sub_div >> bit_info->prediv_bit) & 0xff; + return sub_clk / (sub_div + 1); + } + + return sub_clk; +} + +unsigned long clock_get_periph_rate(int peripheral) +{ + if (cpu_is_exynos5()) { + if (proid_is_exynos5420() || proid_is_exynos5800()) + return exynos542x_get_periph_rate(peripheral); + return exynos5_get_periph_rate(peripheral); + } else { + return 0; + } }
/* exynos4: return ARM clock frequency */ diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index db24dc0..fe8d38c 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -23,9 +23,17 @@ #define SET_RATIO(x, y) ((y & 0xf) << (x << 4))
enum pll_src_bit { +#if defined (CONFIG_EXYNOS5420) || defined (CONFIG_EXYNOS5800) + EXYNOS_SRC_VPLL = -1, + EXYNOS_SRC_MPLL = 3, + EXYNOS_SRC_EPLL = 6, + EXYNOS_SRC_RPLL, +#else + EXYNOS_SRC_RPLL = -1, EXYNOS_SRC_MPLL = 6, EXYNOS_SRC_EPLL, EXYNOS_SRC_VPLL, +#endif };
unsigned long get_pll_clk(int pllreg);