Dear Eric Nelson,
ensure that transmit and receive buffers are cache-line aligned invalidate cache for each packet as received update receive buffer descriptors one cache line at a time flush cache before transmitting
Original patch by Marek: http://lists.denx.de/pipermail/u-boot/2012-February/117695.html
Signed-off-by: Eric Nelson <eric.nelson at boundarydevices.com>
V2 addresses some concerns from the ML:
- Use readl()/writel() instead of mapped data structure accesses
- Wrong comment style
- &rbd_base[0] == rbd_base
removed 'volatile' from fec_send().
V3 updates from ML (and Marek): consolidated CONFIG_FEC_DATA_ALIGNMENT and CONFIG_FEC_DESC_ALIGNMENT added cache flushes after initialization of TBD/RBD
V4 updates from ML http://lists.denx.de/pipermail/u-boot/2012-March#120139 remove tabs after #define/#if/#error replace CONFIG_FEC_ALIGN with ARCH_DMA_MINALIGN
Acked-by: Marek Vasut marex@denx.de
Didn't I ack some previous version? Maybe I even added tested-by to some previous version ;-)
Best regards, Marek Vasut