On 08/13/2015 08:14 AM, Sergey Temerkhanov wrote:
This patch adds code which sets up 2-level page tables on ARM64 thus extending available VA space. CPUs implementing 64k translation granule are able to use direct PA-VA mapping of the whole 48 bit address space. It also adds the ability to reset the SCTRL register at the very beginning of execution to avoid interference from stale mappings set up by early firmware/loaders/etc.
Signed-off-by: Sergey Temerkhanov s.temerkhanov@gmail.com Signed-off-by: Radha Mohan Chintakuntla rchintakuntla@cavium.com
Changes in v3:
- Reduced code duplication
- Renamed CONFIG_SYS_PTL1_BITS to CONFIG_SYS_PTL2_BITS
- Moved 'reset_sctrl' call to the 'reset' label
- Rebased to the actual upstream tree
- Documented newly added config options
Changes in v2:
- Changed code licensing
- Completed the patchset
arch/arm/cpu/armv8/cache_v8.c | 80 +++++++++++++++++++++++++++++++++++++- arch/arm/cpu/armv8/start.S | 36 +++++++++++++++++ arch/arm/include/asm/armv8/mmu.h | 79 ++++++++++++++++++++++++++++++++++--- arch/arm/include/asm/global_data.h | 1 + arch/arm/include/asm/system.h | 7 ++++ arch/arm/lib/board.c | 6 ++- doc/README.arm64 | 35 ++++++++++++++--- 7 files changed, 229 insertions(+), 15 deletions(-)
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index c22f7b6..00778f2 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -12,6 +12,69 @@ DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_SYS_DCACHE_OFF
+#ifdef CONFIG_SYS_FULL_VA +static void set_ptl1_entry(u64 index, u64 ptl2_entry) +{
- u64 *pgd = (u64 *)gd->arch.tlb_addr;
- u64 value;
- value = ptl2_entry | PTL1_TYPE_TABLE;
- pgd[index] = value;
+}
+static void set_ptl2_block(u64 ptl1, u64 bfn, u64 address, u64 memory_type) +{
- u64 *pmd = (u64 *)ptl1;
- u64 value;
- value = address | PTL2_TYPE_BLOCK | PTL2_BLOCK_AF;
- value |= PMD_ATTRINDX(memory_type);
- pmd[bfn] = value;
+}
+static struct mm_region mem_map[] = CONFIG_SYS_MEM_MAP;
+#define PTL1_ENTRIES CONFIG_SYS_PTL1_ENTRIES +#define PTL2_ENTRIES CONFIG_SYS_PTL2_ENTRIES
+static void setup_pgtables(void) +{
- int l1_e, l2_e;
- unsigned long pmd = 0;
- unsigned long address;
- /* Setup the PMD pointers */
- for (l1_e = 0; l1_e < CONFIG_SYS_MEM_MAP_SIZE; l1_e++) {
gd->arch.pmd_addr[l1_e] = gd->arch.tlb_addr +PTL1_ENTRIES * sizeof(u64);gd->arch.pmd_addr[l1_e] += PTL2_ENTRIES * sizeof(u64) * l1_e;gd->arch.pmd_addr[l1_e] += 0xffffUL;gd->arch.pmd_addr[l1_e] &= ~0xffffUL;- }
- /* Setup the page tables */
- for (l1_e = 0; l1_e < PTL1_ENTRIES; l1_e++) {
if (mem_map[pmd].base ==(uintptr_t)l1_e << PTL2_BITS) {set_ptl1_entry(l1_e, gd->arch.pmd_addr[pmd]);for (l2_e = 0; l2_e < PTL2_ENTRIES; l2_e++) {address = mem_map[pmd].base+ (uintptr_t)l2_e * BLOCK_SIZE;set_ptl2_block(gd->arch.pmd_addr[pmd], l2_e,address, mem_map[pmd].attrs);}pmd++;} else {set_ptl1_entry(l1_e, 0);}- }
+}
+#else
void set_pgtable_section(u64 *page_table, u64 index, u64 section, u64 memory_type) { @@ -22,13 +85,25 @@ void set_pgtable_section(u64 *page_table, u64 index, u64 section, page_table[index] = value; }
+#endif
Sergey,
FYI, we have a patch under review[1], rewriting MMU code for Freescale ARMv8 SoCs. It doesn't conflict with your proposed change, but modifies the common file cache_v8.c.
[1] http://patchwork.ozlabs.org/patch/502980/
York