Hi Lokesh,
On 24.4.2018 14:54, Lokesh Vutla wrote:
The Cortex-R* processors are a mid-range CPUs for use in deeply-embedded, real-time systems. It implements the ARMv7-R architecture, and includes Thumb-2 technology for optimum code density and processing throughput.
Except for MPU(Memory Protection Unit) and few CP15 registers, most of the features are compatible with v7 architecture. This series adds minimal support for v7-R architecture by reusing the v7 support. Also adding support for MPU.
Lokesh Vutla (4): arm: v7: Update VBAR only if available arm: Kconfig: Add entry for MMU arm: v7R: Add support for MPU arm: v7R: Add support for enabling caches
Michal Simek (1): arm: v7R: Add initial support
arch/arm/Kconfig | 33 ++++++++ arch/arm/Makefile | 2 + arch/arm/cpu/armv7/Makefile | 2 + arch/arm/cpu/armv7/mpu_v7r.c | 120 ++++++++++++++++++++++++++++++ arch/arm/cpu/armv7/start.S | 4 + arch/arm/cpu/armv7m/Makefile | 3 +- arch/arm/cpu/armv7m/mpu.c | 41 +--------- arch/arm/include/asm/armv7m_mpu.h | 69 +++++++++++++++++ arch/arm/lib/Makefile | 5 +- arch/arm/lib/cache-cp15.c | 14 +++- 10 files changed, 248 insertions(+), 45 deletions(-) create mode 100644 arch/arm/cpu/armv7/mpu_v7r.c
I have tested your series, also wired MPU (protect one region and try to access it) and with caches on and off (running mtest to see number of iterations and improving numbers with cache on) and nothing is showing any functional fundamental problem.
Thanks, Michal