On Monday 30 June 2008, Yi-Neng Lin (林義能) wrote:
We've got a board powered by 405ep running at 266MHz. Now we want to upgrade the clock rate to 333MHz (model: 3LB333C), can anyone give us some pointers doing this? I've tried to search the mailing list but found nothing quite related. Also there seems to exist very limited ports, if not none, of this model to which I may reference.
There are quite a big number of 405EP board ports. I suspect that some of them are capable of running with 333MHz. The frequencies are usually configured via the I2C bootstrap EEPROM.
Below are questions that are more specific:
- For CPU clock rate configuration, exactly what parameters should I
modify? The suspected ones are FWDV (Feedback Divide) and FBDVB (Forward Divide B) which according to the processor user manual determines the PLLOUT A.
Sure. You need to configure the PLL parameters accordingly. The 405EP users manual should give you all the infos you need.
- SDRAM clocking. I guess the clocking should be adapted to something
like 111MHz (given the 333MHz CPU clock); however, the manual shows there there seems to be only two options, namely 100MHz and 133MHz.
Which SDRAM init code are you using? I suggest that you take a look at cpu/ppc4xx/sdram.c and use this file on your system too. You "only" need to configure some SDRAM chip parameters (for example include/configs/zeus.h):
/* * SDRAM configuration (please see cpu/ppc/sdram.[ch]) */ #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ #define CONFIG_SDRAM_BANK1 1 /* init onboard SDRAM bank 1 */
/* SDRAM timings used in datasheet */ #define CFG_SDRAM_CL 3 /* CAS latency */ #define CFG_SDRAM_tRP 20 /* PRECHARGE command period */ #define CFG_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */ #define CFG_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */ #define CFG_SDRAM_tRFC 66 /* Auto refresh period */
- Clocking of others such as PCI (on-chip PLB clock, sync/async PCI
clock) and serial port. Are they supposed to be modified accordingly? 4. Any other parameters?
You need to make sure that all frequencies are in range.
Best regards, Stefan
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