Hi Anup,
On Mon, Jan 21, 2019 at 2:41 PM Anup Patel Anup.Patel@wdc.com wrote:
-----Original Message----- From: Bin Meng [mailto:bmeng.cn@gmail.com] Sent: Monday, January 21, 2019 11:44 AM To: Anup Patel Anup.Patel@wdc.com Cc: Atish Patra Atish.Patra@wdc.com; Auer, Lukas lukas.auer@aisec.fraunhofer.de; sjg@chromium.org; rick@andestech.com; joe.hershberger@ni.com; yamada.masahiro@socionext.com; paul.walmsley@sifive.com; palmer@sifive.com; hch@infradead.org; u-boot@lists.denx.de; agraf@suse.de Subject: Re: [PATCH v2 00/11] SiFive FU540 Support
Hi Anup,
On Mon, Jan 21, 2019 at 12:04 PM Anup Patel Anup.Patel@wdc.com wrote:
-----Original Message----- From: Atish Patra [mailto:atish.patra@wdc.com] Sent: Monday, January 21, 2019 7:07 AM To: Auer, Lukas lukas.auer@aisec.fraunhofer.de; sjg@chromium.org; bmeng.cn@gmail.com; rick@andestech.com; Anup Patel Anup.Patel@wdc.com; joe.hershberger@ni.com; yamada.masahiro@socionext.com Cc: paul.walmsley@sifive.com; palmer@sifive.com; hch@infradead.org; u- boot@lists.denx.de; agraf@suse.de Subject: Re: [PATCH v2 00/11] SiFive FU540 Support
On 1/20/19 12:34 PM, Auer, Lukas wrote:
Hi Anup,
On Fri, 2019-01-18 at 11:18 +0000, Anup Patel wrote:
This patchset adds SiFive Freedom Unleashed (FU540) support to RISC-V U-Boot.
The patches are based upon latest RISC-V U-Boot tree (git://git.denx.de/u-boot-riscv.git) at commit id 91882c472d8c0aef4db699d3f2de55bf43d4ae4b
All drivers namely: SiFive PRCI, SiFive Serial, and Cadance MACB Ethernet work fine on actual SiFive Unleashed board and QEMU sifive_u machine.
Thanks for working on this! Are you also planning on adding the features of the FSBL to U-Boot to remove it from the boot flow?
That would also mean that adding M-mode capability in U-boot. As of now the expected boot flow is
ZSBL->FSBL------->BBL/OpenSBI--------->U-boot------------->Linux (M mode from ROM) (M mode from DRAM) (S Mode from DRAM) (S
Mode
from DRAM)
This is not the mandated boot flow but running the last stage boot loader from S-mode gives flexibility in virtualization in future.
To elaborate more on what Atish already mentioned, our rationale behind ZSBL->FSBL->BBL/OpenSBI->U-Boot(or Any other general bootloader) is as follows:
- We don't want to replicate FSBL code (DRAM and other system-level
init) in general purpose bootloaders (U-Boot, UEFI/Tianocore, etc) 2. We don't want to replicate SBI runtime implementation in general purpose bootloaders (U-Boot, UEFI/Tianocore, etc) 3. We want to use general purpose bootloader (U-Boot, UEFI/Tianocore, etc) inside Guest/VM (S-mode)
Of course, above boot flow is not mandatory. There could be RISC-V systems where prior booting stages (such as ZSBL and FSBL) don't exist so users have following options:
- Run U-Boot in M-mode for such RISC-V systems and link to OpenSBI
static library for SBI runtime services 2. Run U-Boot in S-mode but do most system-level initialization (including DRAM init) in OpenSBI firmware. In other words, use following booting flow: OpenSBI (M-mode) -> U-Boot (S-mode)
For point1 above, we will first try it with U-Boot M-mode on QEMU Virt machine.
Has the OpenSBI project be started somewhere?
Yes, it exist on Github under https://github.com/riscv
I did not find the project under https://github.com/riscv. Maybe it is an internal one at present?
Currently, OpenSBI is at-par with BBL in-terms of SBI implementation but it is extensible and supports lot more boards/targets namely:
- QEMU virt machine
- QEMU sifive_u machine
- SiFive FU540 Unleashed board
- Kendryte K210 board
We are almost there and just need some more time for finishing touches. We will be making is Public very soon (few more days) so stay tuned.
Of course, we will need help from everyone to make OpenSBI better after all it be a community driver open-source project.
There is SBI extensions spec under discussion which will be added in OpenSBI once it is frozen.
I've recently posted an question regarding "mhartid" access from S-mode in the RISC-V ISA ML [1]. If we cannot fix the issue from the architecture level, then we may have to consider adding "mhartid" emulation in the SBI. I will copy you guys on that email thread.
All of us will be present at up-coming FOSDEM19 to talk about SBI extensions, OpenSBI project, and other stuff.
[1] https://groups.google.com/a/groups.riscv.org/forum/#!topic/isa-dev/13afxTuYI...
Regards, Bin