Add a sysreset driver for the MPC83xx platform.
Reviewed-by: Simon Glass sjg@chromium.org Signed-off-by: Mario Six mario.six@gdsys.cc
---
v2 -> v3: * Added driver file to MAINTAINERS
v1 -> v2: New in v2
--- MAINTAINERS | 1 + arch/powerpc/cpu/mpc83xx/cpu.c | 3 +- drivers/sysreset/Kconfig | 5 ++ drivers/sysreset/Makefile | 9 +- drivers/sysreset/sysreset_mpc83xx.c | 159 ++++++++++++++++++++++++++++++++++++ 5 files changed, 172 insertions(+), 5 deletions(-) create mode 100644 drivers/sysreset/sysreset_mpc83xx.c
diff --git a/MAINTAINERS b/MAINTAINERS index 139f7af26ac..b43e4bc179d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -470,6 +470,7 @@ S: Maintained T: git git://git.denx.de/u-boot-mpc83xx.git F: drivers/ram/mpc83xx_sdram.c F: include/dt-bindings/memory/mpc83xx-sdram.h +F: drivers/sysreset/sysreset_mpc83xx.c F: arch/powerpc/cpu/mpc83xx/ F: arch/powerpc/include/asm/arch-mpc83xx/
diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/cpu.c index 82370b54301..e1d2f2f07cb 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu.c +++ b/arch/powerpc/cpu/mpc83xx/cpu.c @@ -115,6 +115,7 @@ int checkcpu(void) return 0; }
+#ifndef CONFIG_SYSRESET int do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) { @@ -169,7 +170,7 @@ do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
return 1; } - +#endif
/* * Get timebase clock frequency (like cpu_clk in Hz) diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig index a6d48e8a662..fd89e5f474c 100644 --- a/drivers/sysreset/Kconfig +++ b/drivers/sysreset/Kconfig @@ -37,4 +37,9 @@ config SYSRESET_WATCHDOG help Reboot support for generic watchdog reset.
+config SYSRESET_MCP83XX + bool "Enable support MPC83xx SoC family reboot driver" + help + Reboot support for NXP MPC83xx SoCs. + endmenu diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile index 0da58a1cf6a..50a7aef9fd7 100644 --- a/drivers/sysreset/Makefile +++ b/drivers/sysreset/Makefile @@ -3,11 +3,12 @@ # (C) Copyright 2016 Cadence Design Systems Inc.
obj-$(CONFIG_SYSRESET) += sysreset-uclass.o +obj-$(CONFIG_ARCH_ASPEED) += sysreset_ast.o +obj-$(CONFIG_ARCH_ROCKCHIP) += sysreset_rockchip.o +obj-$(CONFIG_ARCH_STI) += sysreset_sti.o +obj-$(CONFIG_SANDBOX) += sysreset_sandbox.o +obj-$(CONFIG_SYSRESET_MCP83XX) += sysreset_mpc83xx.o obj-$(CONFIG_SYSRESET_PSCI) += sysreset_psci.o obj-$(CONFIG_SYSRESET_SYSCON) += sysreset_syscon.o obj-$(CONFIG_SYSRESET_WATCHDOG) += sysreset_watchdog.o -obj-$(CONFIG_ARCH_ROCKCHIP) += sysreset_rockchip.o -obj-$(CONFIG_SANDBOX) += sysreset_sandbox.o -obj-$(CONFIG_ARCH_STI) += sysreset_sti.o obj-$(CONFIG_TARGET_XTFPGA) += sysreset_xtfpga.o -obj-$(CONFIG_ARCH_ASPEED) += sysreset_ast.o diff --git a/drivers/sysreset/sysreset_mpc83xx.c b/drivers/sysreset/sysreset_mpc83xx.c new file mode 100644 index 00000000000..e61777e95f5 --- /dev/null +++ b/drivers/sysreset/sysreset_mpc83xx.c @@ -0,0 +1,159 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2018 + * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc + */ + +#include <common.h> +#include <dm.h> +#include <sysreset.h> + +static void __do_reset(void) +{ + ulong msr; + + immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; + + puts("Resetting the board.\n"); + + /* Interrupts and MMU off */ + msr = mfmsr(); + msr &= ~(MSR_EE | MSR_IR | MSR_DR); + mtmsr(msr); + + /* enable Reset Control Reg */ + out_be32(&immap->reset.rpr, 0x52535445); + sync(); + isync(); + + /* confirm Reset Control Reg is enabled */ + + while (!(in_be32(&immap->reset.rcer) & RCER_CRE)) + ; + + udelay(200); + + /* perform reset, only one bit */ + out_be32(&immap->reset.rcr, RCR_SWHR); +} + +int mpc83xx_sysreset_request(struct udevice *dev, enum sysreset_t type) +{ + switch (type) { + case SYSRESET_WARM: + case SYSRESET_COLD: + __do_reset(); + break; + default: + return -EPROTONOSUPPORT; + } + + return -EINPROGRESS; +} + +#if defined(CONFIG_DISPLAY_AER_FULL) +static int print_83xx_arb_event(int force) +{ + int etype = (gd->arch.arbiter_event_attributes & AEATR_EVENT) + >> AEATR_EVENT_SHIFT; + int mstr_id = (gd->arch.arbiter_event_attributes & AEATR_MSTR_ID) + >> AEATR_MSTR_ID_SHIFT; + int tbst = (gd->arch.arbiter_event_attributes & AEATR_TBST) + >> AEATR_TBST_SHIFT; + int tsize = (gd->arch.arbiter_event_attributes & AEATR_TSIZE) + >> AEATR_TSIZE_SHIFT; + int ttype = (gd->arch.arbiter_event_attributes & AEATR_TTYPE) + >> AEATR_TTYPE_SHIFT; + + if (!force && !gd->arch.arbiter_event_address) + return 0; + + puts("Arbiter Event Status:\n"); + printf(" Event Address: 0x%08lX\n", + gd->arch.arbiter_event_address); + printf(" Event Type: 0x%1x = %s\n", etype, event[etype]); + printf(" Master ID: 0x%02x = %s\n", mstr_id, master[mstr_id]); + printf(" Transfer Size: 0x%1x = %d bytes\n", (tbst << 3) | tsize, + tbst ? (tsize ? tsize : 8) : 16 + 8 * tsize); + printf(" Transfer Type: 0x%02x = %s\n", ttype, transfer[ttype]); + + return gd->arch.arbiter_event_address; +} + +#elif defined(CONFIG_DISPLAY_AER_BRIEF) + +static int print_83xx_arb_event(int force, char *buf, int size) +{ + int res; + + if (!force && !gd->arch.arbiter_event_address) + return 0; + + res = snprintf(buf, size, + "Arbiter Event Status: AEATR=0x%08lX, AEADR=0x%08lX\n", + gd->arch.arbiter_event_attributes, + gd->arch.arbiter_event_address); + + return res; +} +#endif /* CONFIG_DISPLAY_AER_xxxx */ + +int mpc83xx_sysreset_get_status(struct udevice *dev, char *buf, int size) +{ + int res; + static const struct { + ulong mask; + char *desc; + } bits[] = { + { + RSR_SWSR, "Software Soft"}, { + RSR_SWHR, "Software Hard"}, { + RSR_JSRS, "JTAG Soft"}, { + RSR_CSHR, "Check Stop"}, { + RSR_SWRS, "Software Watchdog"}, { + RSR_BMRS, "Bus Monitor"}, { + RSR_SRS, "External/Internal Soft"}, { + RSR_HRS, "External/Internal Hard"} + }; + static int n = ARRAY_SIZE(bits); + ulong rsr = gd->arch.reset_status; + int i; + char *sep; + + res = snprintf(buf, size, "Reset Status:"); + if (!res) + return -EIO; + + buf += res; + size -= res; + + sep = " "; + for (i = 0; i < n; i++) + if (rsr & bits[i].mask) { + res = snprintf(buf, size, "%s%s%s", sep, bits[i].desc, (i == n - 1) ? "\n" : ""); + buf += res; + size -= res; + sep = ", "; + } + +/* TODO(mario.six@gdsys.cc): Move this into a dedicated arbiter driver */ +#if defined(CONFIG_DISPLAY_AER_FULL) || defined(CONFIG_DISPLAY_AER_BRIEF) + res = print_83xx_arb_event(rsr & RSR_BMRS, buf, size); + buf += res; + size -= res; +#endif + snprintf(buf, size, "\n"); + + return 0; +} + +static struct sysreset_ops mpc83xx_sysreset = { + .request = mpc83xx_sysreset_request, + .get_status = mpc83xx_sysreset_get_status, +}; + +U_BOOT_DRIVER(sysreset_mpc83xx) = { + .name = "mpc83xx_sysreset", + .id = UCLASS_SYSRESET, + .ops = &mpc83xx_sysreset, +}; -- 2.11.0