4 May
2017
4 May
'17
6:50 p.m.
On 3 May 2017 at 07:07, Álvaro Fernández Rojas noltari@gmail.com wrote:
This SoC has one gpio bank divided into two 32 bit registers, with a total of 52 GPIOs.
Signed-off-by: Álvaro Fernández Rojas noltari@gmail.com
arch/mips/dts/brcm,bcm63268.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)
Reviewed-by: Simon Glass sjg@chromium.org