Enable the Intel clock driver and modify coral's device tree to use it.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
arch/x86/cpu/apollolake/Kconfig | 3 +++ arch/x86/dts/chromebook_coral.dts | 6 ++++++ 2 files changed, 9 insertions(+)
diff --git a/arch/x86/cpu/apollolake/Kconfig b/arch/x86/cpu/apollolake/Kconfig index fcff176c27..ec9f993808 100644 --- a/arch/x86/cpu/apollolake/Kconfig +++ b/arch/x86/cpu/apollolake/Kconfig @@ -39,6 +39,9 @@ config INTEL_APOLLOLAKE imply HAVE_X86_FIT imply INTEL_GPIO imply SMP + imply CLK + imply CMD_CLK + imply CLK_INTEL
if INTEL_APOLLOLAKE
diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts index 24fcbb5063..8802e7a9f6 100644 --- a/arch/x86/dts/chromebook_coral.dts +++ b/arch/x86/dts/chromebook_coral.dts @@ -15,6 +15,7 @@ #include "flashmap-16mb-rw.dtsi" #endif
+#include <dt-bindings/clock/intel-clock.h> #include <asm/intel_pinctrl_defs.h> #include <asm/arch-apollolake/cpu.h> #include <asm/arch-apollolake/gpio.h> @@ -39,6 +40,11 @@ stdout-path = &serial; };
+ clk: clock { + compatible = "intel,apl-clk"; + #clock-cells = <1>; + }; + cpus { u-boot,dm-pre-reloc; #address-cells = <1>;