From: Hugo Villeneuve hvilleneuve@dimonoff.com
While testing the ethernet interface on a Variscite symphony carrier board using an imx8mn SOM with an onboard ADIN1300 PHY (EC hardware configuration), the ethernet PHY is not detected.
The ADIN1300 datasheet indicate that the "Management interface active (t4)" state is reached at most 5ms after the reset signal is deasserted.
The device tree in Variscite custom git repository uses the following property:
phy-reset-post-delay = <20>;
Add a new MDIO property 'reset-deassert-us' of 20ms to have the same delay inside the ethphy node. Adding this property fixes the problem with the PHY detection.
Note that this SOM can also have an Atheros AR8033 PHY. In this case, a 1ms deassert delay is sufficient. Add a comment to that effect.
Fixes: c4c1ed68c1e8 ("imx8mn_var_som: Add support for Variscite VAR-SOM-MX8M-NANO board")
Signed-off-by: Hugo Villeneuve hvilleneuve@dimonoff.com --- arch/arm/dts/imx8mn-var-som.dtsi | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/imx8mn-var-som.dtsi b/arch/arm/dts/imx8mn-var-som.dtsi index dea9eff3f0..4eb578a03f 100644 --- a/arch/arm/dts/imx8mn-var-som.dtsi +++ b/arch/arm/dts/imx8mn-var-som.dtsi @@ -102,11 +102,17 @@ #address-cells = <1>; #size-cells = <0>;
- ethphy: ethernet-phy@4 { + ethphy: ethernet-phy@4 { /* AR8033 or ADIN1300 */ compatible = "ethernet-phy-ieee802.3-c22"; reg = <4>; reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; reset-assert-us = <10000>; + /* + * Deassert delay: + * ADIN1300 requires 5ms. + * AR8033 requires 1ms. + */ + reset-deassert-us = <20000>; }; }; };