L2 Auxiliary Control Register provides configuration and control options for the L2 memory system. Bit 3 of L2ACTLR stands for clean/evict push to external. Setting bit 3 disables clean/evict which is what this patch intends to do.
Signed-off-by: Akshay Saraswat akshay.s@samsung.com Reviewed-by: Simon Glass sjg@chromium.org Tested-by: Simon Glass sjg@chromium.org --- Changes since v1: - Added Reviewed-by & Tested-by.
arch/arm/cpu/armv7/exynos/soc.c | 9 +++++++++ 1 file changed, 9 insertions(+)
diff --git a/arch/arm/cpu/armv7/exynos/soc.c b/arch/arm/cpu/armv7/exynos/soc.c index 8c7d7d8..7268b9b 100644 --- a/arch/arm/cpu/armv7/exynos/soc.c +++ b/arch/arm/cpu/armv7/exynos/soc.c @@ -45,6 +45,15 @@ static void exynos5_set_l2cache_params(void) CACHE_DATA_RAM_LATENCY;
asm volatile("mcr p15, 1, %0, c9, c0, 2\n" : : "r"(val)); + +#ifdef CONFIG_EXYNOS5420 + /* Read CP15 L2ACTLR value */ + asm volatile("mrc p15, 1, %0, c15, c0, 0" : "=r" (val)); + /* Disable clean/evict push to external */ + val |= (0x1 << 3); + /* Write new vlaue to L2ACTLR */ + asm volatile("mcr p15, 1, %0, c15, c0, 0" : : "r" (val)); +#endif }
/*