On Wed, Apr 4, 2018 at 7:26 AM, Ivan Gorinov ivan.gorinov@intel.com wrote:
On Tue, Apr 03, 2018 at 06:17:42AM -0600, Andy Shevchenko wrote:
If readq() is defined as two read operations in 32-bit code, main counter rollover (low part overflow, high part increment) can happen between them.
And how this contradicts ther current code?
It just does not make the code simpler,
...b/c you misread what I suggested.
rollover check is still required if U-Boot is compiled as 32-bit code. Can we do something like the following?
Yes, but... why? What's wrong with replacing two sequential 32-bit reads with one 64-bit?
Doesn't readX/writeX imply a single I/O operation? It may be misleading to define it as two.
Assuming MMX or SSE2 to be supported by all x86 processors, 64-bit I/O registers can be accessed as a single operation even in 32-bit code:
Adding such requirement (MMX or SSE2) to U-Boot is not good. Why do we require MMX or SSE2 for readq? Can we use general purpose registers?
static inline u64 readq(void *addr) { u64 value;
asm volatile ("movq (%0), %%xmm0" : : "r" (addr)); asm volatile ("movq %%xmm0, %0" : "=m" (value)); return value;}
I can add these definitions to "asm/io.h".
Regards, Bin