This patch adds initialization of the UPMC RAM to support up to two Intel 82527 compatible CAN controller on the TQM85xx modules.
Signed-off-by: Thomas Waehner thomas.waehner@tqs.de Signed-off-by: Wolfgang Grandegger wg@grandegger.com --- board/tqc/tqm85xx/law.c | 4 +++ board/tqc/tqm85xx/tlb.c | 1 + board/tqc/tqm85xx/tqm85xx.c | 59 +++++++++++++++++++++++++++++++++++++++++++ include/configs/TQM85xx.h | 11 ++++++++ include/mpc85xx.h | 5 +++ 5 files changed, 80 insertions(+), 0 deletions(-)
diff --git a/board/tqc/tqm85xx/law.c b/board/tqc/tqm85xx/law.c index d937700..ad35464 100644 --- a/board/tqc/tqm85xx/law.c +++ b/board/tqc/tqm85xx/law.c @@ -35,6 +35,7 @@ * 0xc000_0000 0xdfff_ffff RapidIO 512M * 0xe000_0000 0xe000_ffff CCSR 1M * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M + * 0xe300_0000 0xe3ff_ffff CAN 16M * 0xf800_0000 0xf80f_ffff BCSR 1M * 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M * @@ -49,6 +50,9 @@ struct law_entry law_table[] = { SET_LAW_ENTRY (3, CFG_LBC_FLASH_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC), SET_LAW_ENTRY (4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), SET_LAW_ENTRY (5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), +#ifdef CONFIG_CAN_DRIVER + SET_LAW_ENTRY (6, CFG_CAN_BASE, LAWAR_SIZE_16M, LAW_TRGT_IF_LBC), +#endif /* CONFIG_CAN_DRIVER */ };
int num_law_entries = ARRAY_SIZE (law_table); diff --git a/board/tqc/tqm85xx/tlb.c b/board/tqc/tqm85xx/tlb.c index 3e29062..dc36201 100644 --- a/board/tqc/tqm85xx/tlb.c +++ b/board/tqc/tqm85xx/tlb.c @@ -95,6 +95,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 6: 64M Non-cacheable, guarded * 0xe0000000 1M CCSRBAR * 0xe2000000 16M PCI1 IO + * 0xe3000000 16M CAN */ SET_TLB_ENTRY (1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, diff --git a/board/tqc/tqm85xx/tqm85xx.c b/board/tqc/tqm85xx/tqm85xx.c index f38b009..bca59a3 100644 --- a/board/tqc/tqm85xx/tqm85xx.c +++ b/board/tqc/tqm85xx/tqm85xx.c @@ -31,6 +31,7 @@ #include <pci.h> #include <asm/processor.h> #include <asm/immap_85xx.h> +#include <asm/io.h> #include <ioports.h> #include <flash.h>
@@ -333,6 +334,28 @@ int misc_init_r (void) return 0; }
+#ifdef CONFIG_CAN_DRIVER +/* + * Initialize UPMC RAM + */ +static void upmc_write (u_char addr, uint val) +{ + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); + + out_be32 (&lbc->mdr, val); + + out_be32 (&lbc->mcmr, + (in_be32 (&lbc->mcmr) & ~(MxMR_OP_NORM | MxMR_MAD)) | + MxMR_OP_WARR | (addr & MxMR_MAD)); + /* dummy access to perform write */ + out_8 ((void __iomem *)CFG_CAN_BASE, 0); + + /* normal operation */ + out_be32 (&lbc->mcmr, + (in_be32 (&lbc->mcmr) & ~MxMR_OP_WARR) | MxMR_OP_NORM); +} +#endif /* CONFIG_CAN_DRIVER */ + /* * Initialize Local Bus */ @@ -389,6 +412,42 @@ void local_bus_init (void) gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000); asm ("sync;isync;msync"); } + +#ifdef CONFIG_CAN_DRIVER + /* Initialize OR2 / BR2 */ + lbc->or2 = CFG_OR2_CAN; + lbc->br2 = CFG_BR2_CAN; + + /* + * According to timing specifications EAD must be + * set if Local Bus Clock is > 83 MHz. + */ + if (lbc_hz > 83) + lbc->or2 |= ORxU_EAD; + + /* LGPL4 is UPWAIT */ + out_be32(&lbc->mcmr, MxMR_DSx_3_CYCL | MxMR_GPL4_DIS | MxMR_WLFx_3X); + + /* Initialize UPMC for CAN: single read */ + upmc_write (0x00, 0xFFFFED00); + upmc_write (0x01, 0xCCFFCC00); + upmc_write (0x02, 0x00FFCF00); + upmc_write (0x03, 0x00FFCF00); + upmc_write (0x04, 0x00FFDC00); + upmc_write (0x05, 0x00FFCF00); + upmc_write (0x06, 0x00FFED00); + upmc_write (0x07, 0x3FFFCC07); + + /* Initialize UPMC for CAN: single write */ + upmc_write (0x18, 0xFFFFED00); + upmc_write (0x19, 0xCCFFEC00); + upmc_write (0x1A, 0x00FFED80); + upmc_write (0x1B, 0x00FFED80); + upmc_write (0x1C, 0x00FFFC00); + upmc_write (0x1D, 0x0FFFEC00); + upmc_write (0x1E, 0x0FFFEF00); + upmc_write (0x1F, 0x3FFFEC05); +#endif /* CONFIG_CAN_DRIVER */ }
#if defined(CONFIG_PCI) diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index 4011b2a..9eec858 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -52,6 +52,8 @@
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
+#undef CONFIG_CAN_DRIVER /* CAN Driver support */ + /* * sysclk for MPC85xx * @@ -199,6 +201,15 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif
+/* CAN */ +#ifdef CONFIG_CAN_DRIVER +#define CFG_CAN_BASE 0xE3000000 /* CAN base address */ +#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 KiB address mask */ +#define CFG_OR2_CAN (CFG_CAN_OR_AM | ORxU_BI) +#define CFG_BR2_CAN ((CFG_CAN_BASE & BRx_BA_MSK) | \ + BRx_PS_8 | BRx_MS_UPMC | BRx_V) +#endif /* CONFIG_CAN_DRIVER */ + /* * I2C */ diff --git a/include/mpc85xx.h b/include/mpc85xx.h index 321b24f..9dbc9a8 100644 --- a/include/mpc85xx.h +++ b/include/mpc85xx.h @@ -53,7 +53,12 @@ #define ORxU_AM_MSK 0xffff8000 /* Address Mask Mask */
#define MxMR_OP_NORM 0x00000000 /* Normal Operation */ +#define MxMR_MAD 0x0000003F /* Machine address, RAM address ptr*/ +#define MxMR_WLFx_3X 0x00000C00 /* Write loop executed 3 times */ +#define MxMR_GPL4_DIS 0x00040000 /* GPL4 output line disable */ #define MxMR_DSx_2_CYCL 0x00400000 /* 2 cycle Disable Period */ +#define MxMR_DSx_3_CYCL 0x00800000 /* 3 cycle Disable Period */ +#define MxMR_DSx_4_CYCL 0x00C00000 /* 4 cycle Disable Period */ #define MxMR_OP_WARR 0x10000000 /* Write to Array */ #define MxMR_BSEL 0x80000000 /* Bus Select */