On Tue, 31 Oct 2023 at 19:52, Caleb Connolly caleb.connolly@linaro.org wrote:
Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom.
Signed-off-by: Caleb Connolly caleb.connolly@linaro.org
arch/arm/Kconfig | 1 + arch/arm/mach-ipq40xx/Makefile | 8 - arch/arm/mach-ipq40xx/pinctrl-snapdragon.c | 166 --------------------- arch/arm/mach-ipq40xx/pinctrl-snapdragon.h | 30 ---- drivers/pinctrl/qcom/Kconfig | 7 + drivers/pinctrl/qcom/Makefile | 1 + .../pinctrl/qcom}/pinctrl-ipq4019.c | 25 +++- 7 files changed, 28 insertions(+), 210 deletions(-)
I would expect this to be the 2nd patch in this series. Apart from that feel free to add:
Acked-by: Sumit Garg sumit.garg@linaro.org
-Sumit
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index faccfaf720a8..23daed70aac9 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -767,6 +767,7 @@ config ARCH_IPQ40XX select SMEM select OF_CONTROL select CLK_QCOM_IPQ4019
select PINCTRL_QCOM_IPQ4019 imply CMD_DMconfig ARCH_KEYSTONE diff --git a/arch/arm/mach-ipq40xx/Makefile b/arch/arm/mach-ipq40xx/Makefile deleted file mode 100644 index b36a935c6f9f..000000000000 --- a/arch/arm/mach-ipq40xx/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (c) 2019 Sartura Ltd. -# -# Author: Robert Marko robert.marko@sartura.hr
-obj-y += pinctrl-snapdragon.o -obj-y += pinctrl-ipq4019.o diff --git a/arch/arm/mach-ipq40xx/pinctrl-snapdragon.c b/arch/arm/mach-ipq40xx/pinctrl-snapdragon.c deleted file mode 100644 index 036fec93d727..000000000000 --- a/arch/arm/mach-ipq40xx/pinctrl-snapdragon.c +++ /dev/null @@ -1,166 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/*
- TLMM driver for Qualcomm IPQ40xx
- (C) Copyright 2018 Ramon Fried ramon.fried@gmail.com
- Copyright (c) 2020 Sartura Ltd.
- Author: Robert Marko robert.marko@sartura.hr
- */
-#include <common.h> -#include <dm.h> -#include <errno.h> -#include <asm/io.h> -#include <dm/device_compat.h> -#include <dm/lists.h> -#include <dm/pinctrl.h> -#include <linux/bitops.h> -#include "pinctrl-snapdragon.h"
-struct msm_pinctrl_priv {
phys_addr_t base;struct msm_pinctrl_data *data;-};
-#define GPIO_CONFIG_OFFSET(x) ((x) * 0x1000) -#define TLMM_GPIO_PULL_MASK GENMASK(1, 0) -#define TLMM_FUNC_SEL_MASK GENMASK(5, 2) -#define TLMM_DRV_STRENGTH_MASK GENMASK(8, 6) -#define TLMM_GPIO_DISABLE BIT(9)
-static const struct pinconf_param msm_conf_params[] = {
{ "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 2 },{ "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },{ "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 2 },-};
-static int msm_get_functions_count(struct udevice *dev) -{
struct msm_pinctrl_priv *priv = dev_get_priv(dev);return priv->data->functions_count;-}
-static int msm_get_pins_count(struct udevice *dev) -{
struct msm_pinctrl_priv *priv = dev_get_priv(dev);return priv->data->pin_count;-}
-static const char *msm_get_function_name(struct udevice *dev,
unsigned int selector)-{
struct msm_pinctrl_priv *priv = dev_get_priv(dev);return priv->data->get_function_name(dev, selector);-}
-static int msm_pinctrl_probe(struct udevice *dev) -{
struct msm_pinctrl_priv *priv = dev_get_priv(dev);priv->base = devfdt_get_addr(dev);priv->data = (struct msm_pinctrl_data *)dev->driver_data;return priv->base == FDT_ADDR_T_NONE ? -EINVAL : 0;-}
-static const char *msm_get_pin_name(struct udevice *dev, unsigned int selector) -{
struct msm_pinctrl_priv *priv = dev_get_priv(dev);return priv->data->get_pin_name(dev, selector);-}
-static int msm_pinmux_set(struct udevice *dev, unsigned int pin_selector,
unsigned int func_selector)-{
struct msm_pinctrl_priv *priv = dev_get_priv(dev);clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),TLMM_FUNC_SEL_MASK | TLMM_GPIO_DISABLE,priv->data->get_function_mux(func_selector) << 2);return 0;-}
-static int msm_pinconf_set(struct udevice *dev, unsigned int pin_selector,
unsigned int param, unsigned int argument)-{
struct msm_pinctrl_priv *priv = dev_get_priv(dev);switch (param) {case PIN_CONFIG_DRIVE_STRENGTH:clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),TLMM_DRV_STRENGTH_MASK, argument << 6);break;case PIN_CONFIG_BIAS_DISABLE:clrbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),TLMM_GPIO_PULL_MASK);break;case PIN_CONFIG_BIAS_PULL_UP:clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),TLMM_GPIO_PULL_MASK, argument);break;default:return 0;}return 0;-}
-static int msm_pinctrl_bind(struct udevice *dev) -{
ofnode node = dev_ofnode(dev);const char *name;int ret;ofnode_get_property(node, "gpio-controller", &ret);if (ret < 0)return 0;/* Get the name of gpio node */name = ofnode_get_name(node);if (!name)return -EINVAL;/* Bind gpio node */ret = device_bind_driver_to_node(dev, "gpio_msm",name, node, NULL);if (ret)return ret;dev_dbg(dev, "bind %s\n", name);return 0;-}
-static struct pinctrl_ops msm_pinctrl_ops = {
.get_pins_count = msm_get_pins_count,.get_pin_name = msm_get_pin_name,.set_state = pinctrl_generic_set_state,.pinmux_set = msm_pinmux_set,.pinconf_num_params = ARRAY_SIZE(msm_conf_params),.pinconf_params = msm_conf_params,.pinconf_set = msm_pinconf_set,.get_functions_count = msm_get_functions_count,.get_function_name = msm_get_function_name,-};
-static const struct udevice_id msm_pinctrl_ids[] = {
{ .compatible = "qcom,ipq4019-pinctrl", .data = (ulong)&ipq4019_data },{ }-};
-U_BOOT_DRIVER(pinctrl_snapdraon) = {
.name = "pinctrl_msm",.id = UCLASS_PINCTRL,.of_match = msm_pinctrl_ids,.priv_auto = sizeof(struct msm_pinctrl_priv),.ops = &msm_pinctrl_ops,.probe = msm_pinctrl_probe,.bind = msm_pinctrl_bind,-}; diff --git a/arch/arm/mach-ipq40xx/pinctrl-snapdragon.h b/arch/arm/mach-ipq40xx/pinctrl-snapdragon.h deleted file mode 100644 index 2341a713495d..000000000000 --- a/arch/arm/mach-ipq40xx/pinctrl-snapdragon.h +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/*
- Qualcomm Pin control
- (C) Copyright 2018 Ramon Fried ramon.fried@gmail.com
- */
-#ifndef _PINCTRL_SNAPDRAGON_H -#define _PINCTRL_SNAPDRAGON_H
-#include <common.h>
-struct msm_pinctrl_data {
int pin_count;int functions_count;const char *(*get_function_name)(struct udevice *dev,unsigned int selector);unsigned int (*get_function_mux)(unsigned int selector);const char *(*get_pin_name)(struct udevice *dev,unsigned int selector);-};
-struct pinctrl_function {
const char *name;int val;-};
-extern struct msm_pinctrl_data ipq4019_data;
-#endif diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 412925c48788..2fe639814785 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -20,6 +20,13 @@ config PINCTRL_QCOM_APQ8096 Say Y here to enable support for pinctrl on the MSM8996 / APQ8096 Snapdragon 820 SoC, as well as the associated GPIO driver.
+config PINCTRL_QCOM_IPQ4019
bool "Qualcomm IPQ4019 GCC"select PINCTRL_QCOMhelpSay Y here to enable support for pinctrl on the IPQ4019 SoC,as well as the associated GPIO driver.config PINCTRL_QCOM_QCS404 bool "Qualcomm QCS404 GCC" select PINCTRL_QCOM diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 86f507427301..6d9aca6d7b7e 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -4,6 +4,7 @@
obj-$(CONFIG_PINCTRL_QCOM) += pinctrl-qcom.o obj-$(CONFIG_PINCTRL_QCOM_APQ8016) += pinctrl-apq8016.o +obj-$(CONFIG_PINCTRL_QCOM_IPQ4019) += pinctrl-ipq4019.o obj-$(CONFIG_PINCTRL_QCOM_APQ8096) += pinctrl-apq8096.o obj-$(CONFIG_PINCTRL_QCOM_QCS404) += pinctrl-qcs404.o obj-$(CONFIG_PINCTRL_QCOM_SDM845) += pinctrl-sdm845.o diff --git a/arch/arm/mach-ipq40xx/pinctrl-ipq4019.c b/drivers/pinctrl/qcom/pinctrl-ipq4019.c similarity index 71% rename from arch/arm/mach-ipq40xx/pinctrl-ipq4019.c rename to drivers/pinctrl/qcom/pinctrl-ipq4019.c index 3e365f8cc86a..2d99f99e1e45 100644 --- a/arch/arm/mach-ipq40xx/pinctrl-ipq4019.c +++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c @@ -7,12 +7,13 @@
- Author: Robert Marko robert.marko@sartura.hr
*/
-#include "pinctrl-snapdragon.h" #include <common.h> +#include <dm.h>
+#include "pinctrl-qcom.h"
#define MAX_PIN_NAME_LEN 32 -static char pin_name[MAX_PIN_NAME_LEN];
+static char pin_name[MAX_PIN_NAME_LEN] __section(".data"); static const struct pinctrl_function msm_pinctrl_functions[] = { {"gpio", 0}, {"blsp_uart0_0", 1}, /* Only for GPIO:16,17 */ @@ -26,7 +27,6 @@ static const struct pinctrl_function msm_pinctrl_functions[] = { {"mdc_0", 1}, /* Only for GPIO7 */ {"mdc_1", 2}, /* Only for GPIO52 */ };
static const char *ipq4019_get_function_name(struct udevice *dev, unsigned int selector) { @@ -45,10 +45,23 @@ static unsigned int ipq4019_get_function_mux(unsigned int selector) return msm_pinctrl_functions[selector].val; }
-struct msm_pinctrl_data ipq4019_data = {
.pin_count = 100,+static const struct msm_pinctrl_data ipq4019_data = {
.pin_data = { .pin_count = 100, }, .functions_count = ARRAY_SIZE(msm_pinctrl_functions), .get_function_name = ipq4019_get_function_name, .get_function_mux = ipq4019_get_function_mux, .get_pin_name = ipq4019_get_pin_name,};
+static const struct udevice_id msm_pinctrl_ids[] = {
{ .compatible = "qcom,ipq4019-pinctrl", .data = (ulong)&ipq4019_data },{ /* Sentinal */ }+};
+U_BOOT_DRIVER(pinctrl_ipq4019) = {
.name = "pinctrl_ipq4019",.id = UCLASS_NOP,.of_match = msm_pinctrl_ids,.ops = &msm_pinctrl_ops,.bind = msm_pinctrl_bind,+};
-- 2.42.0