On Mon, 2016-09-05 at 18:06 +0200, Marek Vasut wrote:
On 08/22/2016 05:02 PM, Chin Liang See wrote:
Add support for Stratix 10 SoC development kit
Signed-off-by: Chin Liang See clsee@altera.com Cc: Marek Vasut marex@denx.de Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Ley Foon Tan lftan@altera.com
arch/arm/Kconfig | 7 +- arch/arm/mach-socfpga/Kconfig | 10 +++ configs/socfpga_stratix10_defconfig | 14 ++++ include/configs/socfpga_stratix10_socdk.h | 135 ++++++++++++++++++++++++++++++ 4 files changed, 163 insertions(+), 3 deletions(-) create mode 100755 configs/socfpga_stratix10_defconfig create mode 100644 include/configs/socfpga_stratix10_socdk.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index aef901c..c8e8767 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -600,10 +600,11 @@ config ARCH_SNAPDRAGON
config ARCH_SOCFPGA bool "Altera SOCFPGA family"
- select CPU_V7
- select SUPPORT_SPL
- select CPU_V7 if !TARGET_SOCFPGA_STRATIX10
- select ARM64 if TARGET_SOCFPGA_STRATIX10
- select SUPPORT_SPL if !TARGET_SOCFPGA_STRATIX10 select OF_CONTROL
- select SPL_OF_CONTROL
- select SPL_OF_CONTROL if !TARGET_SOCFPGA_STRATIX10
Why is the SPL disabled ?
We will be having SPL for Stratix 10. It will added in later days as SPL main function is for DDR setup. This is not needed for SOC Virtual Platform now.
select DM select DM_SPI_FLASH select DM_SPI diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach -socfpga/Kconfig index 1a43c7b..4e3b238 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -11,6 +11,9 @@ config TARGET_SOCFPGA_CYCLONE5 config TARGET_SOCFPGA_GEN5 bool
+config TARGET_SOCFPGA_STRATIX10
- bool
choice prompt "Altera SOCFPGA board select" optional @@ -51,6 +54,10 @@ config TARGET_SOCFPGA_TERASIC_SOCKIT bool "Terasic SoCkit (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5
+config TARGET_SOCFPGA_STRATIX10_SOCDK
- bool "Altera SOCFPGA SoCDK (Stratix 10)"
- select TARGET_SOCFPGA_STRATIX10
endchoice
config SYS_BOARD @@ -63,6 +70,7 @@ config SYS_BOARD default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES default "sr1500" if TARGET_SOCFPGA_SR1500 default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
- default "stratix10-socdk" if
TARGET_SOCFPGA_STRATIX10_SOCDK
Keep all the lists sorted .
Noted, will fix this.
config SYS_VENDOR default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK @@ -72,6 +80,7 @@ config SYS_VENDOR default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
- default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK
config SYS_SOC default "socfpga" @@ -86,5 +95,6 @@ config SYS_CONFIG_NAME default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500 default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
- default "socfpga_stratix10_socdk" if
TARGET_SOCFPGA_STRATIX10_SOCDK
endif
[...]
btw. what about Arria 10 ? Will it ever land ? And will I ever get a kit ? :)
Since S10 is good, I will help out the A10 upstreaming once S10 is intergrated. While for dev kit, let me work that out as we have A10 dev kit with production silicon :)
Thanks Chin Liang