This series is to: 1. Enable ECC priming with BIST engine (Patch 1) 2. Add a function to store base address and size of RAM's banks in a 64 bit device private data (Patch 2) 3. Setup the ECC region start and range (Patch 3) 4. Enable ECC 1 bit error, 2 bit error and multiple bit error interrupts (Patch 4) 5. Add CONFIG_K3_INLINE_ECC (Patch 5) 6. Pull the redundant DDR functions to a common location (Patch 6) 7. Remove redundant DDR functions (Patch 7, 8) 8. Fixup DDR size when ECC is enabled (Patch 9) 9. Add ss_cfg reg entry (Patch 10)
Tested on AM62X and AM62A, results: AM62X: https://gist.github.com/santhosh21/c5f07cd921bd2b12d12385f22c698ee6 AM62A: https://gist.github.com/santhosh21/e5fa684d890d65b4034346435213ec8b
Things to look in the test log: 1. Time-taken for priming 2. Fixed up DDR size (RAM size =- ECC reserved space).
Thanks and Regards, Santhosh.
Georgi Vlaev (1): ram: k3-ddrss: Use the DDR controller BIST engine for ECC priming
Neha Malcom Francis (1): drivers: ram: Kconfig: Add CONFIG_K3_INLINE_ECC
Santhosh Kumar K (8): ram: k3-ddrss: Add k3_ddrss_ddr_bank_base_size_calc() to solve 'calculations restricted to 32 bits' issue ram: k3-ddrss: Setup ECC region start and range ram: k3-ddrss: Enable ECC interrupts board: ti: common: k3-ddr-init: Pull redundant DDR functions to a common location board: ti: am64x: evm: Remove redundant DDR functions board: ti: am62x: evm: Remove redundant DDR functions board: ti: am62ax: evm: Fixup DDR size when ECC is enabled arm: dts: k3-am62a-ddr: Add ss_cfg reg entry
arch/arm/dts/k3-am62a-ddr.dtsi | 7 +- board/ti/am62ax/evm.c | 16 +-- board/ti/am62x/evm.c | 61 +--------- board/ti/am64x/evm.c | 71 +---------- board/ti/common/k3-ddr-init.c | 75 ++++++++++++ board/ti/common/k3-ddr-init.h | 15 +++ drivers/ram/Kconfig | 11 ++ drivers/ram/k3-ddrss/k3-ddrss.c | 209 +++++++++++++++++++++++++++----- 8 files changed, 307 insertions(+), 158 deletions(-) create mode 100644 board/ti/common/k3-ddr-init.c create mode 100644 board/ti/common/k3-ddr-init.h