[U-Boot] [PATCH v4 4/7] ARM: dts: rockchip: ADD dp83867 CLK_OUT muxing

The CLK_O_SEL default is synchronus to XI input clock, which is 25 MHz. Set CLK_O_SEL to channel A transmit clock so we have 125 MHz on CLK_OUT.

Signed-off-by: Janine Hagemann j.hagemann@phytec.de --- v4: No changes --- arch/arm/dts/rk3288-phycore-som.dtsi | 1 + 1 file changed, 1 insertion(+)

diff --git a/arch/arm/dts/rk3288-phycore-som.dtsi b/arch/arm/dts/rk3288-phycore-som.dtsi index 02d1196..2dba0aa 100644 --- a/arch/arm/dts/rk3288-phycore-som.dtsi +++ b/arch/arm/dts/rk3288-phycore-som.dtsi @@ -191,6 +191,7 @@ ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; enet-phy-lane-no-swap; + ti,clk-output-sel = <DP83867_CLK_O_SEL_CHN_A_TCLK>; }; }; };