
19 Feb
2015
19 Feb
'15
10:04 a.m.
One more thing...
On Mon, Feb 16, 2015 at 01:54:46PM +0100, Jan Kiszka wrote:
diff --git a/arch/arm/cpu/armv7/tegra-common/psci.S b/arch/arm/cpu/armv7/tegra-common/psci.S
[...]
+ENTRY(psci_arch_init)
- mov r6, lr
- mrc p15, 0, r5, c1, c1, 0 @ Read SCR
- bic r5, r5, #1 @ Secure mode
- mcr p15, 0, r5, c1, c1, 0 @ Write SCR
- isb
- @ lock reset vector
- ldr r4, =TEGRA_SB_CSR_0
- ldr r5, [r4]
- orr r5, r5, #NS_RST_VEC_WR_DIS
- str r5, [r4]
Perhaps extend the comment to mention that this locks the reset vector for accesses from non-secure mode, otherwise it might be confusing that psci_cpu_on actually writes the reset vector.
Thierry