On Tue, Oct 22, 2019 at 1:55 AM Simon Glass sjg@chromium.org wrote:
On Mon, 21 Oct 2019 at 01:55, Andy Shevchenko andy.shevchenko@gmail.com wrote:
On Mon, Oct 21, 2019 at 6:32 AM Simon Glass sjg@chromium.org wrote:
Thanks for doing this! Common comment, please do not limit LPSS drivers, including GPIO / pin control, to be Appololake only. They must be available for entire Intel Skylake family of SoCs (basically all of them from Skylake, with maybe few exceptions).
I have certainly put some code in intel_common, but until we have a Skylake it is a pain to figure out what is common, etc.
Clearly the GPIO code can be common, but it is very easy to move it when we have the next thing.
I can move GPIO and LPSS over to common, for now.
Yes, please! That is exactly my concern. Thanks!