Marek Vasut marex@denx.de schrieb am Di., 11. Juni 2019, 16:01:
On 6/10/19 8:31 AM, Ley Foon Tan wrote:
On Thu, May 30, 2019 at 5:03 PM Ley Foon Tan ley.foon.tan@intel.com
wrote:
This is 2nd version of patchset to add Intel Agilex SoC[1] support. This patchset needs to apply after patch in [2] for Designware i2c
clock from DM.
Intel Agilex SoC is with a 64-bit quad core ARM Cortex-A53 MPCore hard processor system (HPS). New IPs in Agilex are CCU, clock manager
and SDRAM,
other IPs have minor changes compared to Stratix 10.
Intel Agilex HPS TRM:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/...
v1->v2:
- Change clock driver to DM
- Reuse base_addr_s10.h from S10
- Add system_manager_s10_agilex_common.h
- Update commit message for CCU patch
- Update Linux commit id in dts/dtsi patch
Any comment on this v2 patch series?
I'd like to see a review from Dinh or Simon.
That's on my list. Sorry, but I'm really really short on time for U-Boot, lately :-(
I'll see what I can do to review it soon.
Regards, Simon