Looks good to me.
Acked-by: Jaehoon Chung jh80.chung@samsung.com
On 10/29/2013 04:23 PM, Rajeshwari S Shinde wrote:
SMDK5420 has a new Security Management Unit added for dwmmc driver, hence, configuring the control registers to support booting via eMMC.
Signed-off-by: Alim Akhtar alim.akhtar@samsung.com Signed-off-by: Rajeshwari Shinde rajeshwari.s@samsung.com Acked-by: Simon Glass sjg@chromium.org
Changes in V3:
- New patch.
Changes in V4: Added flag to dissble SMU Changes in V5:
- None
Changes in V6:
- Moved the SMU definitions to arch/arm dwmmc.h
arch/arm/include/asm/arch-exynos/dwmmc.h | 13 +++++++++++++ drivers/mmc/dw_mmc.c | 11 +++++++++++ drivers/mmc/exynos_dw_mmc.c | 3 +++ include/dwmmc.h | 3 +++ 4 files changed, 30 insertions(+)
diff --git a/arch/arm/include/asm/arch-exynos/dwmmc.h b/arch/arm/include/asm/arch-exynos/dwmmc.h index b9eca76..d1c5d4f 100644 --- a/arch/arm/include/asm/arch-exynos/dwmmc.h +++ b/arch/arm/include/asm/arch-exynos/dwmmc.h @@ -14,6 +14,19 @@ #define DWMCI_SET_DRV_CLK(x) ((x) << 16) #define DWMCI_SET_DIV_RATIO(x) ((x) << 24)
+#define EMMCP_MPSBEGIN0 0x1200 +#define EMMCP_SEND0 0x1204 +#define EMMCP_CTRL0 0x120C
+#define MPSCTRL_SECURE_READ_BIT (0x1<<7) +#define MPSCTRL_SECURE_WRITE_BIT (0x1<<6) +#define MPSCTRL_NON_SECURE_READ_BIT (0x1<<5) +#define MPSCTRL_NON_SECURE_WRITE_BIT (0x1<<4) +#define MPSCTRL_USE_FUSE_KEY (0x1<<3) +#define MPSCTRL_ECB_MODE (0x1<<2) +#define MPSCTRL_ENCRYPTION (0x1<<1) +#define MPSCTRL_VALID (0x1<<0)
#ifdef CONFIG_OF_CONTROL int exynos_dwmmc_init(const void *blob); #endif diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index 9a803a0..a3506d4 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -11,6 +11,7 @@ #include <mmc.h> #include <dwmmc.h> #include <asm-generic/errno.h> +#include <asm/arch/dwmmc.h>
#define PAGE_SIZE 4096
@@ -301,6 +302,16 @@ static int dwmci_init(struct mmc *mmc) struct dwmci_host *host = (struct dwmci_host *)mmc->priv; u32 fifo_size;
if (host->quirks & DWMCI_QUIRK_DISABLE_SMU) {
dwmci_writel(host, EMMCP_MPSBEGIN0, 0);dwmci_writel(host, EMMCP_SEND0, 0);dwmci_writel(host, EMMCP_CTRL0,MPSCTRL_SECURE_READ_BIT |MPSCTRL_SECURE_WRITE_BIT |MPSCTRL_NON_SECURE_READ_BIT |MPSCTRL_NON_SECURE_WRITE_BIT | MPSCTRL_VALID);}
dwmci_writel(host, DWMCI_PWREN, 1);
if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) {
diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c index 4ef9fec..f7439a0 100644 --- a/drivers/mmc/exynos_dw_mmc.c +++ b/drivers/mmc/exynos_dw_mmc.c @@ -62,6 +62,9 @@ int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel) host->name = "EXYNOS DWMMC"; host->ioaddr = (void *)regbase; host->buswidth = bus_width; +#ifdef CONFIG_EXYNOS5420
- host->quirks = DWMCI_QUIRK_DISABLE_SMU;
+#endif
if (clksel) { host->clksel_val = clksel; diff --git a/include/dwmmc.h b/include/dwmmc.h index 08ced0b..6263140 100644 --- a/include/dwmmc.h +++ b/include/dwmmc.h @@ -123,6 +123,9 @@ #define DWMCI_BMOD_IDMAC_FB (1 << 1) #define DWMCI_BMOD_IDMAC_EN (1 << 7)
+/* quirks */ +#define DWMCI_QUIRK_DISABLE_SMU (1 << 0)
struct dwmci_host { char *name; void *ioaddr;