[U-Boot-Users] POST: 8xx cache basic test #2

Hi All,

I'm writing POST cache tests for MPC82xx. I'm trying to maintain the same "objectives" of the tests found in post/cache_8xx.S, but I need some clarification:

Basic test #2 (post/cache_8xx.S) does the following:

1. turn on the data cache 2. switch the data cache to write-back mode 3. invalidate the data cache 4. write the zero pattern to a cached area 5. turn off the data cache 6. write the negative pattern to the area 7. turn on the data cache 8. read the area (confirm negative pattern)

At step 6, the data cache is disabled, so it operates as if accessing a cache-inhibited region. i.e. - the data is written to memory, but not to cache, and the cache status bits are not affected.

Clarification needed here: At step 8, I would expect to read the zero pattern unless disabling/enabling the data cache affects the status bits. What's actually happening?

Thanks, --Scott