On 01/27/2016 03:18 PM, Måns Rullgård wrote:
Chin Liang See clsee@altera.com writes:
On Wed, 2016-01-27 at 13:46 +0000, Måns Rullgård wrote:
Chin Liang See clsee@altera.com writes:
On Fri, 2016-01-22 at 10:35 -0600, Dinh Nguyen wrote:
On 01/21/2016 10:31 AM, Marek Vasut wrote:
On Thursday, January 21, 2016 at 05:20:33 PM, Måns Rullgård wrote: > Tom Rini trini@konsulko.com writes: >> On Wed, Jan 20, 2016 at 08:31:30PM +0000, Måns Rullgård >> wrote: >>> I'm having a problem with u-boot 2016.01 failing to >>> detect the FPGA on my Altera Cyclone V SoC Development >>> Kit. On startup, it simply prints "FPGA: Not Altera chip >>> ID" (the ID having been read as all -zero). No amount of >>> messing with jumpers or switches makes a difference. The >>> software on the SD card included in the box appears to >>> work, so on a whim I took the SPL pre-loader from this >>> card and combined it with the main 2016.01 u-boot. This >>> makes the detection succeed, despite Marek baulking at >>> this idea. The "good" SPL identifies as "U-Boot SPL >>> 2013.01.01 (Dec 04 2014 - 08:59:41)" which is a different >>> build date than the main u-boot on the same SD card, so >>> which source code version it was built from is anyone's >>> guess. >>> >>> What's interesting is that Marek's board works with u >>> -boot 2016.01 while mine fails even with the very same >>> binary. The boards are different revisions (his >>> 100-0321003-C1, mine -E1), and the main Cyclone V chips >>> are also different (his 5CSXFC6D6F31C8NES, mine >>> 5CSXFC6D6F31C6N). >>> >>> Any suggestions for what to try next? >> v2016.01 release or to of tree? If top of tree, try >> http://patchwork.ozlabs.org/patch/570009/ > Tried release, top of tree, and top of tree with that patch. > Nothing works.
Both part number is different in speed grade. This is first time I heard about this issue. A quick suspect might due to clock. Can you try to copy pll_config.h that is passing (from 2013.01.01) and replace the one in 2016?
That doesn't work at all. Now it fails to detect the FPGA, then hangs after printing the amount of DRAM.
Can you share with me the pll_config for 2013.01.01 that is working for you?
I don't know that it is. The only thing I've found to work is the unidentified SPL on the SD card that came with the dev kit.
I pushed some DDR fixes into u-boot-socfpga/ddr branch [1], which fixed DDR calibration issue on a board I have in here. Can you try them ? Thanks
[1] http://git.denx.de/?p=u-boot/u-boot-socfpga.git;a=shortlog;h=refs/heads/ddr