I've got an old STx AMC8548 board. It came with u-boot-1.1.4 which works. I upgraded it to stock u-boot-1.3.4 which also works. However, nothing newer will, despite a lot of effort I spent in a last couple of days.
The crux of the problem: cpu gets a weird "program error" exception out of nowhere and gets stuck indefinitely.
It seems to always break down after relocation to RAM. The last print-out before "relocate_code" is always printed, the first print-out in "board_init_r" only on random occasions. With single stepping the odds of reaching past the first print-out in "board_init_r" improve, but not by much. Sometimes, print-outs are passed by but nothing is written to the serial port.
I tried running DDR memory tests - all ok. Manual inspection through debugger (I've got BDI3000) shows no apparent problems (all is set up in RAM correctly). Writing to serial port through debugger works, even after CPU halt.
May be somebody has any idea what can it be?
Here's typical printout for u-boot-2009.06 (2009.03 behaves exactly the same), with partial debug enabled:
U-Boot 2009.06 (Jul 24 2009 - 19:33:07)
CPU: 8548E, Version: 1.1, (0x80390011) Core: E500, Version: 1.0, (0x80210010) Clock Configuration: CPU0:660 MHz, CCB:264 MHz, DDR:132 MHz (264 MT/s data rate), LBC:16.500 MHz L1: D-cache 32 kB enabled I-cache 32 kB enabled Board: STX AMC8548 I2C: ready DRAM: Initializing starting at step 1 (STEP_GET_SPD) DDR: DDR II rank density = 0xe4013c72 mclk_ps = 7580 i=0, x = 0, lowest_tCKmin_found = 0 i=1, x = 5000, lowest_tCKmin_found = 0 i=2, x = 3750, lowest_tCKmin_found = 5000 i=3, x = 3000, lowest_tCKmin_found = 5000 i=4, x = 2500, lowest_tCKmin_found = 5000 lowest_tCKmin_CL = 3 Computing lowest common DIMM parameters for memctl=0 using mclk_ps = 7580 checking common caslat = 5 CL = 5 ok on DIMM 0 at tCK=7580 ps with its tCKmin_X_ps of 3750 checking common caslat = 4 CL = 4 ok on DIMM 0 at tCK=7580 ps with its tCKmin_X_minus_1_ps of 3750 checking common caslat = 3 CL = 3 ok on DIMM 0 at tCK=7580 ps with its tCKmin_X_minus_2_ps of 5000 lowest common SPD-defined CAS latency = 3 highest common dereated CAS latency = 3 Warning: not all DIMMs ECC capable, cant enable ECC setting additive_latency to 2 because it was greater than tRCD_ps Error: invalid additive latency exceeds tRCD(min). Reloading memory controller configuration options for memctl=0 mclk_ps = 7580 ps FSL Memory ctrl cg register computation FSLDDR: cs[0]_bnds = 0x0000000f FSLDDR: cs[0]_config = 0x80010102 FSLDDR: cs[0]_config_2 = 0x00000000 FSLDDR: cs[1]_bnds = 0x0010001f FSLDDR: cs[1]_config = 0x80010102 FSLDDR: cs[1]_config_2 = 0x00000000 FSLDDR: timing_cfg_0 = 0x00220802 FSLDDR: timing_cfg_3 = 0x00000000 FSLDDR: timing_cfg_1 = 0x26256222 FSLDDR: timing_cfg_2 = 0x05104d05 FSLDDR: ddr_sdram_cfg = 0xc3000000 DDR: ddr_data_init = 0xdeadbeef FSLDDR: ddr_sdram_cfg_2 = 0x24401010 FSLDDR: ddr_sdram_mode = 0x00440232 FSLDDR: ddr_sdram_mode_2 = 0x00000000 FSLDDR: ddr_sdram_interval = 0x04060100 FSLDDR: timing_cfg_4 = 0x00000000 FSLDDR: timing_cfg_5 = 0x00000000 Programming controller 0 total_memory = 536870912 DDR: 512 MB SDRAM test range 1ff00000 - 20000000 SDRAM test phase 1: SDRAM test phase 2: SDRAM test passed. Top of RAM usable for U-Boot at: 20000000 Reserving 245k for U-Boot at: 1ffc0000 Reserving 128k for malloc() at: 1ffa0000 Reserving 80 Bytes for Board Info at: 1ff9ffb0 Reserving 68 Bytes for Global Data at: 1ff9ff6c Stack Pointer at: 1ff9ff48 New Stack Pointer is: 1ff9ff48
--- cpu halted ---