Add an I2C driver for the Rockchip RK3288, using driver model. It should work for other Rockchip SoCs also.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v4: - Rename pinctrl.h to dm/pinctrl.h
Changes in v3: None Changes in v2: None
arch/arm/include/asm/arch-rockchip/i2c.h | 70 ++++++ drivers/i2c/Kconfig | 9 + drivers/i2c/Makefile | 1 + drivers/i2c/rk_i2c.c | 391 +++++++++++++++++++++++++++++++ 4 files changed, 471 insertions(+) create mode 100644 arch/arm/include/asm/arch-rockchip/i2c.h create mode 100644 drivers/i2c/rk_i2c.c
diff --git a/arch/arm/include/asm/arch-rockchip/i2c.h b/arch/arm/include/asm/arch-rockchip/i2c.h new file mode 100644 index 0000000..d81f8ff --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/i2c.h @@ -0,0 +1,70 @@ +/* + * (C) Copyright 2012 SAMSUNG Electronics + * Jaehoon Chung jh80.chung@samsung.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_I2C_H +#define __ASM_ARCH_I2C_H + +struct i2c_regs { + u32 con; + u32 clkdiv; + u32 mrxaddr; + u32 mrxraddr; + u32 mtxcnt; + u32 mrxcnt; + u32 ien; + u32 ipd; + u32 fcnt; + u32 reserved0[0x37]; + u32 txdata[8]; + u32 reserved1[0x38]; + u32 rxdata[8]; +}; + +/* Control register */ +#define I2C_CON_EN (1 << 0) +#define I2C_CON_MOD(mod) ((mod) << 1) +#define I2C_MODE_TX 0x00 +#define I2C_MODE_TRX 0x01 +#define I2C_MODE_RX 0x02 +#define I2C_MODE_RRX 0x03 +#define I2C_CON_MASK (3 << 1) + +#define I2C_CON_START (1 << 3) +#define I2C_CON_STOP (1 << 4) +#define I2C_CON_LASTACK (1 << 5) +#define I2C_CON_ACTACK (1 << 6) + +/* Clock dividor register */ +#define I2C_CLKDIV_VAL(divl, divh) \ + (((divl) & 0xffff) | (((divh) << 16) & 0xffff0000)) + +/* the slave address accessed for master rx mode */ +#define I2C_MRXADDR_SET(vld, addr) (((vld) << 24) | (addr)) + +/* the slave register address accessed for master rx mode */ +#define I2C_MRXRADDR_SET(vld, raddr) (((vld) << 24) | (raddr)) + +/* interrupt enable register */ +#define I2C_BTFIEN (1 << 0) +#define I2C_BRFIEN (1 << 1) +#define I2C_MBTFIEN (1 << 2) +#define I2C_MBRFIEN (1 << 3) +#define I2C_STARTIEN (1 << 4) +#define I2C_STOPIEN (1 << 5) +#define I2C_NAKRCVIEN (1 << 6) + +/* interrupt pending register */ +#define I2C_BTFIPD (1 << 0) +#define I2C_BRFIPD (1 << 1) +#define I2C_MBTFIPD (1 << 2) +#define I2C_MBRFIPD (1 << 3) +#define I2C_STARTIPD (1 << 4) +#define I2C_STOPIPD (1 << 5) +#define I2C_NAKRCVIPD (1 << 6) +#define I2C_IPD_ALL_CLEAN 0x7f + +#endif diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index c40bd5c..14adda2 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -58,6 +58,15 @@ config DM_I2C_GPIO bindings are supported. Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt
+config SYS_I2C_ROCKCHIP + bool "Rockchip I2C driver" + depends on DM_I2C + help + Add support for the Rockchip I2C driver. This is used with various + Rockchip parts such as RK3126, RK3128, RK3036 and RK3288. All chips + have several I2C ports and all are provided, controled by the + device tree. + config SYS_I2C_SANDBOX bool "Sandbox I2C driver" depends on SANDBOX && DM_I2C diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 9b45248..8ce294b 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -31,6 +31,7 @@ obj-$(CONFIG_SYS_I2C_OMAP24XX) += omap24xx_i2c.o obj-$(CONFIG_SYS_I2C_OMAP34XX) += omap24xx_i2c.o obj-$(CONFIG_SYS_I2C_PPC4XX) += ppc4xx_i2c.o obj-$(CONFIG_SYS_I2C_RCAR) += rcar_i2c.o +obj-$(CONFIG_SYS_I2C_ROCKCHIP) += rk_i2c.o obj-$(CONFIG_SYS_I2C_S3C24X0) += s3c24x0_i2c.o obj-$(CONFIG_SYS_I2C_SANDBOX) += sandbox_i2c.o i2c-emul-uclass.o obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o diff --git a/drivers/i2c/rk_i2c.c b/drivers/i2c/rk_i2c.c new file mode 100644 index 0000000..ebdba35 --- /dev/null +++ b/drivers/i2c/rk_i2c.c @@ -0,0 +1,391 @@ +/* + * (C) Copyright 2015 Google, Inc + * + * (C) Copyright 2008-2014 Rockchip Electronics + * Peter, Software Engineering, superpeter.cai@gmail.com. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <errno.h> +#include <i2c.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/i2c.h> +#include <asm/arch/periph.h> +#include <dm/pinctrl.h> +#include <linux/sizes.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* i2c timerout */ +#define I2C_TIMEOUT_MS 100 +#define I2C_RETRY_COUNT 3 + +/* rk i2c fifo max transfer bytes */ +#define RK_I2C_FIFO_SIZE 32 + +struct rk_i2c { + struct udevice *clk; + struct udevice *pinctrl; + struct i2c_regs *regs; + unsigned int speed; + enum periph_id id; +}; + +static inline void rk_i2c_get_div(int div, int *divh, int *divl) +{ + *divl = div / 2; + if (div % 2 == 0) + *divh = div / 2; + else + *divh = DIV_ROUND_UP(div, 2); +} + +/* + * SCL Divisor = 8 * (CLKDIVL+1 + CLKDIVH+1) + * SCL = PCLK / SCLK Divisor + * i2c_rate = PCLK + */ +static void rk_i2c_set_clk(struct rk_i2c *i2c, uint32_t scl_rate) +{ + uint32_t i2c_rate; + int div, divl, divh; + + /* First get i2c rate from pclk */ + i2c_rate = clk_get_periph_rate(i2c->clk, i2c->id); + + div = DIV_ROUND_UP(i2c_rate, scl_rate * 8) - 2; + divh = 0; + divl = 0; + if (div >= 0) + rk_i2c_get_div(div, &divh, &divl); + writel(I2C_CLKDIV_VAL(divl, divh), &i2c->regs->clkdiv); + + debug("rk_i2c_set_clk: i2c rate = %d, scl rate = %d\n", i2c_rate, + scl_rate); + debug("set i2c clk div = %d, divh = %d, divl = %d\n", div, divh, divl); + debug("set clk(I2C_CLKDIV: 0x%08x)\n", readl(&i2c->regs->clkdiv)); +} + +static void rk_i2c_show_regs(struct i2c_regs *regs) +{ +#ifdef DEBUG + uint i; + + debug("i2c_con: 0x%08x\n", readl(®s->con)); + debug("i2c_clkdiv: 0x%08x\n", readl(®s->clkdiv)); + debug("i2c_mrxaddr: 0x%08x\n", readl(®s->mrxaddr)); + debug("i2c_mrxraddR: 0x%08x\n", readl(®s->mrxraddr)); + debug("i2c_mtxcnt: 0x%08x\n", readl(®s->mtxcnt)); + debug("i2c_mrxcnt: 0x%08x\n", readl(®s->mrxcnt)); + debug("i2c_ien: 0x%08x\n", readl(®s->ien)); + debug("i2c_ipd: 0x%08x\n", readl(®s->ipd)); + debug("i2c_fcnt: 0x%08x\n", readl(®s->fcnt)); + for (i = 0; i < 8; i++) + debug("i2c_txdata%d: 0x%08x\n", i, readl(®s->txdata[i])); + for (i = 0; i < 8; i++) + debug("i2c_rxdata%d: 0x%08x\n", i, readl(®s->rxdata[i])); +#endif +} + +static int rk_i2c_send_start_bit(struct rk_i2c *i2c) +{ + struct i2c_regs *regs = i2c->regs; + ulong start; + + debug("I2c Send Start bit.\n"); + writel(I2C_IPD_ALL_CLEAN, ®s->ipd); + + writel(I2C_CON_EN | I2C_CON_START, ®s->con); + writel(I2C_STARTIEN, ®s->ien); + + start = get_timer(0); + while (1) { + if (readl(®s->ipd) & I2C_STARTIPD) { + writel(I2C_STARTIPD, ®s->ipd); + break; + } + if (get_timer(start) > I2C_TIMEOUT_MS) { + debug("I2C Send Start Bit Timeout\n"); + rk_i2c_show_regs(regs); + return -ETIMEDOUT; + } + udelay(1); + } + + return 0; +} + +static int rk_i2c_send_stop_bit(struct rk_i2c *i2c) +{ + struct i2c_regs *regs = i2c->regs; + ulong start; + + debug("I2c Send Stop bit.\n"); + writel(I2C_IPD_ALL_CLEAN, ®s->ipd); + + writel(I2C_CON_EN | I2C_CON_STOP, ®s->con); + writel(I2C_CON_STOP, ®s->ien); + + start = get_timer(0); + while (1) { + if (readl(®s->ipd) & I2C_STOPIPD) { + writel(I2C_STOPIPD, ®s->ipd); + break; + } + if (get_timer(start) > I2C_TIMEOUT_MS) { + debug("I2C Send Start Bit Timeout\n"); + rk_i2c_show_regs(regs); + return -ETIMEDOUT; + } + udelay(1); + } + + return 0; +} + +static inline void rk_i2c_disable(struct rk_i2c *i2c) +{ + writel(0, &i2c->regs->con); +} + +static int rk_i2c_read(struct rk_i2c *i2c, uchar chip, uint reg, uint r_len, + uchar *buf, uint b_len) +{ + struct i2c_regs *regs = i2c->regs; + uchar *pbuf = buf; + uint bytes_remain_len = b_len; + uint bytes_xferred = 0; + uint words_xferred = 0; + ulong start; + uint con = 0; + uint rxdata; + uint i, j; + int err; + + debug("rk_i2c_read: chip = %d, reg = %d, r_len = %d, b_len = %d\n", + chip, reg, r_len, b_len); + + err = rk_i2c_send_start_bit(i2c); + if (err) + return err; + + writel(I2C_MRXADDR_SET(1, chip << 1 | 1), ®s->mrxaddr); + if (r_len == 0) { + writel(0, ®s->mrxraddr); + } else if (r_len < 4) { + writel(I2C_MRXRADDR_SET(r_len, reg), ®s->mrxraddr); + } else { + debug("I2C Read: addr len %d not supported\n", r_len); + return -EIO; + } + + while (bytes_remain_len) { + if (bytes_remain_len > RK_I2C_FIFO_SIZE) { + con = I2C_CON_EN | I2C_CON_MOD(I2C_MODE_TRX); + bytes_xferred = 32; + } else { + con = I2C_CON_EN | I2C_CON_MOD(I2C_MODE_TRX) | + I2C_CON_LASTACK; + bytes_xferred = bytes_remain_len; + } + words_xferred = DIV_ROUND_UP(bytes_xferred, 4); + + writel(con, ®s->con); + writel(bytes_xferred, ®s->mrxcnt); + writel(I2C_MBRFIEN | I2C_NAKRCVIEN, ®s->ien); + + start = get_timer(0); + while (1) { + if (readl(®s->ipd) & I2C_NAKRCVIPD) { + writel(I2C_NAKRCVIPD, ®s->ipd); + err = -EREMOTEIO; + } + if (readl(®s->ipd) & I2C_MBRFIPD) { + writel(I2C_MBRFIPD, ®s->ipd); + break; + } + if (get_timer(start) > I2C_TIMEOUT_MS) { + debug("I2C Read Data Timeout\n"); + err = -ETIMEDOUT; + rk_i2c_show_regs(regs); + goto i2c_exit; + } + udelay(1); + } + + for (i = 0; i < words_xferred; i++) { + rxdata = readl(®s->rxdata[i]); + debug("I2c Read RXDATA[%d] = 0x%x\n", i, rxdata); + for (j = 0; j < 4; j++) { + if ((i * 4 + j) == bytes_xferred) + break; + *pbuf++ = (rxdata >> (j * 8)) & 0xff; + } + } + + bytes_remain_len -= bytes_xferred; + debug("I2C Read bytes_remain_len %d\n", bytes_remain_len); + } + +i2c_exit: + rk_i2c_send_stop_bit(i2c); + rk_i2c_disable(i2c); + + return err; +} + +static int rk_i2c_write(struct rk_i2c *i2c, uchar chip, uint reg, uint r_len, + uchar *buf, uint b_len) +{ + struct i2c_regs *regs = i2c->regs; + int err; + uchar *pbuf = buf; + uint bytes_remain_len = b_len + r_len + 1; + uint bytes_xferred = 0; + uint words_xferred = 0; + ulong start; + uint txdata; + uint i, j; + + debug("rk_i2c_write: chip = %d, reg = %d, r_len = %d, b_len = %d\n", + chip, reg, r_len, b_len); + err = rk_i2c_send_start_bit(i2c); + if (err) + return err; + + while (bytes_remain_len) { + if (bytes_remain_len > RK_I2C_FIFO_SIZE) + bytes_xferred = 32; + else + bytes_xferred = bytes_remain_len; + words_xferred = DIV_ROUND_UP(bytes_xferred, 4); + + for (i = 0; i < words_xferred; i++) { + txdata = 0; + for (j = 0; j < 4; j++) { + if ((i * 4 + j) == bytes_xferred) + break; + + if (i == 0 && j == 0) { + txdata |= (chip << 1); + } else if (i == 0 && j <= r_len) { + txdata |= (reg & + (0xff << ((j - 1) * 8))) << 8; + } else { + txdata |= (*pbuf++)<<(j * 8); + } + writel(txdata, ®s->txdata[i]); + } + debug("I2c Write TXDATA[%d] = 0x%x\n", i, txdata); + } + + writel(I2C_CON_EN | I2C_CON_MOD(I2C_MODE_TX), ®s->con); + writel(bytes_xferred, ®s->mtxcnt); + writel(I2C_MBTFIEN | I2C_NAKRCVIEN, ®s->ien); + + start = get_timer(0); + while (1) { + if (readl(®s->ipd) & I2C_NAKRCVIPD) { + writel(I2C_NAKRCVIPD, ®s->ipd); + err = -EREMOTEIO; + } + if (readl(®s->ipd) & I2C_MBTFIPD) { + writel(I2C_MBTFIPD, ®s->ipd); + break; + } + if (get_timer(start) > I2C_TIMEOUT_MS) { + debug("I2C Write Data Timeout\n"); + err = -ETIMEDOUT; + rk_i2c_show_regs(regs); + goto i2c_exit; + } + udelay(1); + } + + bytes_remain_len -= bytes_xferred; + debug("I2C Write bytes_remain_len %d\n", bytes_remain_len); + } + +i2c_exit: + rk_i2c_send_stop_bit(i2c); + rk_i2c_disable(i2c); + + return err; +} + +static int rockchip_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, + int nmsgs) +{ + struct rk_i2c *i2c = dev_get_priv(bus); + int ret; + + debug("i2c_xfer: %d messages\n", nmsgs); + for (; nmsgs > 0; nmsgs--, msg++) { + debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len); + if (msg->flags & I2C_M_RD) { + ret = rk_i2c_read(i2c, msg->addr, 0, 0, msg->buf, + msg->len); + } else { + ret = rk_i2c_write(i2c, msg->addr, 0, 0, msg->buf, + msg->len); + } + if (ret) { + debug("i2c_write: error sending\n"); + return -EREMOTEIO; + } + } + + return 0; +} + +int rockchip_i2c_set_bus_speed(struct udevice *bus, unsigned int speed) +{ + struct rk_i2c *i2c = dev_get_priv(bus); + + rk_i2c_set_clk(i2c, speed); + + return 0; +} + +static int rockchip_i2c_probe(struct udevice *bus) +{ + struct rk_i2c *i2c = dev_get_priv(bus); + int ret; + + ret = uclass_get_device(UCLASS_PINCTRL, 0, &i2c->pinctrl); + if (ret) + return ret; + ret = uclass_get_device(UCLASS_CLK, 0, &i2c->clk); + if (ret) + return ret; + ret = pinctrl_get_periph_id(i2c->pinctrl, bus); + if (ret < 0) + return ret; + i2c->id = ret; + i2c->regs = (void *)dev_get_addr(bus); + return pinctrl_request(i2c->pinctrl, i2c->id, 0); +} + +static const struct dm_i2c_ops rockchip_i2c_ops = { + .xfer = rockchip_i2c_xfer, + .set_bus_speed = rockchip_i2c_set_bus_speed, +}; + +static const struct udevice_id rockchip_i2c_ids[] = { + { .compatible = "rockchip,rk3288-i2c" }, + { } +}; + +U_BOOT_DRIVER(i2c_rockchip) = { + .name = "i2c_rockchip", + .id = UCLASS_I2C, + .of_match = rockchip_i2c_ids, + .probe = rockchip_i2c_probe, + .priv_auto_alloc_size = sizeof(struct rk_i2c), + .ops = &rockchip_i2c_ops, +};