Re: [PATCH v3 11/23] clk: add clock driver for MediaTek MT7620 SoC

On 09.11.20 09:25, Weijie Gao wrote:

This patch adds a clock driver for MediaTek MT7620 SoC. This driver provides clock gate control as well as getting clock frequency for CPU/SYS/XTAL and some peripherals.

Signed-off-by: Weijie Gao weijie.gao@mediatek.com

Reviewed-by: Stefan Roese sr@denx.de

Thanks, Stefan

---

v3 changes: none v2 changes: none

---

drivers/clk/mtmips/Makefile | 1 + drivers/clk/mtmips/clk-mt7620.c | 159 +++++++++++++++++++++++++ include/dt-bindings/clock/mt7620-clk.h | 40 +++++++ 3 files changed, 200 insertions(+) create mode 100644 drivers/clk/mtmips/clk-mt7620.c create mode 100644 include/dt-bindings/clock/mt7620-clk.h

diff --git a/drivers/clk/mtmips/Makefile b/drivers/clk/mtmips/Makefile index e1938418da..732e7f2545 100644 --- a/drivers/clk/mtmips/Makefile +++ b/drivers/clk/mtmips/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0

+obj-$(CONFIG_SOC_MT7620) += clk-mt7620.o obj-$(CONFIG_SOC_MT7628) += clk-mt7628.o diff --git a/drivers/clk/mtmips/clk-mt7620.c b/drivers/clk/mtmips/clk-mt7620.c new file mode 100644 index 0000000000..44e4b53c21 --- /dev/null +++ b/drivers/clk/mtmips/clk-mt7620.c @@ -0,0 +1,159 @@ +// SPDX-License-Identifier: GPL-2.0 +/*

• • Copyright (C) 2020 MediaTek Inc. All Rights Reserved.
• • Author: Weijie Gao weijie.gao@mediatek.com
• */

+#include <clk-uclass.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <dt-bindings/clock/mt7620-clk.h> +#include <misc.h> +#include <mach/mt7620-sysc.h>

+/* CLKCFG1 */ +#define CLKCFG1_REG 0x30

+#define CLK_SRC_CPU -1 +#define CLK_SRC_CPU_D2 -2 +#define CLK_SRC_SYS -3 +#define CLK_SRC_XTAL -4 +#define CLK_SRC_PERI -5

+struct mt7620_clk_priv {

• struct udevice *dev;
• struct udevice *sysc;
• struct mt7620_sysc_clks clks;

+};

+static const int mt7620_clks[] = {

• [CLK_SYS] = CLK_SRC_SYS,
• [CLK_CPU] = CLK_SRC_CPU,
• [CLK_XTAL] = CLK_SRC_XTAL,
• [CLK_MIPS_CNT] = CLK_SRC_CPU_D2,
• [CLK_UARTF] = CLK_SRC_PERI,
• [CLK_UARTL] = CLK_SRC_PERI,
• [CLK_SPI] = CLK_SRC_SYS,
• [CLK_I2C] = CLK_SRC_PERI,
• [CLK_I2S] = CLK_SRC_PERI,

+};

+static ulong mt7620_clk_get_rate(struct clk *clk) +{

• struct mt7620_clk_priv *priv = dev_get_priv(clk->dev);
• if (clk->id >= ARRAY_SIZE(mt7620_clks))

• return 0;
  

• switch (mt7620_clks[clk->id]) {
• case CLK_SRC_CPU:

• return priv->clks.cpu_clk;
  

• case CLK_SRC_CPU_D2:

• return priv->clks.cpu_clk / 2;
  

• case CLK_SRC_SYS:

• return priv->clks.sys_clk;
  

• case CLK_SRC_XTAL:

• return priv->clks.xtal_clk;
  

• case CLK_SRC_PERI:

• return priv->clks.peri_clk;
  

• default:

• return mt7620_clks[clk->id];
  

• }

+}

+static int mt7620_clkcfg1_rmw(struct mt7620_clk_priv *priv, u32 clr, u32 set) +{

• u32 val;
• int ret;
• ret = misc_read(priv->sysc, CLKCFG1_REG, &val, sizeof(val));
• if (ret) {

• dev_err(priv->dev, "mt7620_clk: failed to read CLKCFG1\n");
  

• return ret;
  

• }
• val &= ~clr;
• val |= set;
• ret = misc_write(priv->sysc, CLKCFG1_REG, &val, sizeof(val));
• if (ret) {

• dev_err(priv->dev, "mt7620_clk: failed to write CLKCFG1\n");
  

• return ret;
  

• }
• return 0;

+}

+static int mt7620_clk_enable(struct clk *clk) +{

• struct mt7620_clk_priv *priv = dev_get_priv(clk->dev);
• if (clk->id > 30)

• return -1;
  

• return mt7620_clkcfg1_rmw(priv, 0, BIT(clk->id));

+}

+static int mt7620_clk_disable(struct clk *clk) +{

• struct mt7620_clk_priv *priv = dev_get_priv(clk->dev);
• if (clk->id > 30)

• return -1;
  

• return mt7620_clkcfg1_rmw(priv, BIT(clk->id), 0);

+}

+const struct clk_ops mt7620_clk_ops = {

• .enable = mt7620_clk_enable,
• .disable = mt7620_clk_disable,
• .get_rate = mt7620_clk_get_rate,

+};

+static int mt7620_clk_probe(struct udevice *dev) +{

• struct mt7620_clk_priv *priv = dev_get_priv(dev);
• struct ofnode_phandle_args sysc_args;
• int ret;
• ret = ofnode_parse_phandle_with_args(dev->node, "mediatek,sysc", NULL,

• 			     0, 0, &sysc_args);
  

• if (ret) {

• dev_err(dev, "mt7620_clk: sysc property not found\n");
  

• return ret;
  

• }
• ret = uclass_get_device_by_ofnode(UCLASS_MISC, sysc_args.node,

• 			  &priv->sysc);
  

• if (ret) {

• dev_err(dev, "mt7620_clk: failed to sysc device\n");
  

• return ret;
  

• }
• ret = misc_ioctl(priv->sysc, MT7620_SYSC_IOCTL_GET_CLK,

• 	 &priv->clks);
  

• if (ret) {

• dev_err(dev, "mt7620_clk: failed to get base clocks\n");
  

• return ret;
  

• }
• priv->dev = dev;
• return 0;

+}

+static const struct udevice_id mt7620_clk_ids[] = {

• { .compatible = "mediatek,mt7620-clk" },
• { }

+};

+U_BOOT_DRIVER(mt7620_clk) = {

• .name = "mt7620-clk",
• .id = UCLASS_CLK,
• .of_match = mt7620_clk_ids,
• .probe = mt7620_clk_probe,
• .priv_auto_alloc_size = sizeof(struct mt7620_clk_priv),
• .ops = &mt7620_clk_ops,
• .flags = DM_FLAG_PRE_RELOC,

+}; diff --git a/include/dt-bindings/clock/mt7620-clk.h b/include/dt-bindings/clock/mt7620-clk.h new file mode 100644 index 0000000000..3bb91ebdf1 --- /dev/null +++ b/include/dt-bindings/clock/mt7620-clk.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/*

• • Copyright (C) 2020 MediaTek Inc.
• • Author: Weijie Gao weijie.gao@mediatek.com
• */

+#ifndef _DT_BINDINGS_MT7620_CLK_H_ +#define _DT_BINDINGS_MT7620_CLK_H_

+/* Base clocks */ +#define CLK_SYS 34 +#define CLK_CPU 33 +#define CLK_XTAL 32

+/* Peripheral clocks */ +#define CLK_SDHC 30 +#define CLK_MIPS_CNT 28 +#define CLK_PCIE 26 +#define CLK_UPHY_12M 25 +#define CLK_EPHY 24 +#define CLK_ESW 23 +#define CLK_UPHY_48M 22 +#define CLK_FE 21 +#define CLK_UARTL 19 +#define CLK_SPI 18 +#define CLK_I2S 17 +#define CLK_I2C 16 +#define CLK_NAND 15 +#define CLK_GDMA 14 +#define CLK_PIO 13 +#define CLK_UARTF 12 +#define CLK_PCM 11 +#define CLK_MC 10 +#define CLK_INTC 9 +#define CLK_TIMER 8 +#define CLK_GE2 7 +#define CLK_GE1 6

+#endif /* _DT_BINDINGS_MT7620_CLK_H_ */

Viele Grüße, Stefan