I'm not familiar with the port in question, but using the d-cache as temporary memory when external memory is not yet available is a common trick. As long as you don't need more temporary memory then the size of the cache then you can use the cache itself as a temporary store. The cache is probably set up as read/write allocate, to make sure what you write stays in the cache. Even if its just read allocate you could pre allocate a range to make sure you get a hit when you attempt to access that address.
Its likely the 4000000 maps to nothing yet, most any address will do, just so long as its marked cacheable. I seem to recall the ppc4xx series had both block mapping ability (forget their names, ittr/dttr/ perhaps) and per page mapping available (mmu).
Regards,
Richard W.
-----Original Message----- From: u-boot-users-admin@lists.sourceforge.net [mailto:u-boot-users- admin@lists.sourceforge.net] On Behalf Of Frank Young Sent: Sunday, May 16, 2004 10:38 PM To: u-boot-users@lists.sourceforge.net Subject: [U-Boot-Users] How does the stack works in the DCache?
Hello all,
I am using PPC 405 Walnut with 16M sdram. I got a question regarding
the
DCache setting in u-boot cpu/ppc4xx/start.S. I wrote the pseudo-code
of
start.S as below:
(In File cpu/ppc4xx/start.S) .globl _start _start: _start: clear and set up registers invalidate I and D caches Enable 128M cachable regions set up temporary stack in DCACHE sdram_init() (cpu/ppc4xx/sdram.c)
..........
I understand the code is trying to set up a stack in DCache. But I
didn't
get how the code makes it. Before calling sdram_init(), the stack
pointer
is CFG_INIT_RAM_ADDR = 0x40000000. I suppose this address is not a
physical
address and it refers to the address in the DCache. Is that right? But
the
CFG_INIT_RAM_ADDR is located in the address space of sdram. So is
there
any address translator in between DCache and CFG_INIT_RAM_ADDR? Or did I
miss
anything? I just couldn't figure out how the stack works in DCache...
Can
someone give me any clue? Thanks!
Frank
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