Changed to store QSPI reference clock in kHz instead of Hz in boot scratch cold0 register for Stratix10 and Agilex.
This patch is in preparation for Diamond Mesa SDRAM driver support. Reserved 4 bits for Diamond Mesa SDRAM driver, and there will be 28 bits to store QSPI reference clock. Due to limited bits, QSPI reference clock frequency is converted to kHz from Hz.
Signed-off-by: Siew Chin Lim elly.siew.chin.lim@intel.com Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com --- arch/arm/mach-socfpga/clock_manager.c | 5 ++-- .../include/mach/system_manager_soc64.h | 12 +++++++++- arch/arm/mach-socfpga/mailbox_s10.c | 28 +++++++++++++++++++--- 3 files changed, 39 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c index 2d0cc19f7a..8299d0956d 100644 --- a/arch/arm/mach-socfpga/clock_manager.c +++ b/arch/arm/mach-socfpga/clock_manager.c @@ -66,8 +66,9 @@ int set_cpu_clk_info(void) #if defined(CONFIG_TARGET_SOCFPGA_SOC64) unsigned int cm_get_qspi_controller_clk_hz(void) { - return readl(socfpga_get_sysmgr_addr() + - SYSMGR_SOC64_BOOT_SCRATCH_COLD0); + return (readl(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_BOOT_SCRATCH_COLD0) & + SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK) * 1000; }
#endif diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h index e54ea3b012..cc90e1ad03 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h @@ -42,7 +42,10 @@ void populate_sysmgr_pinmux(void); #define SYSMGR_SOC64_GPO 0xe4 #define SYSMGR_SOC64_GPI 0xe8 #define SYSMGR_SOC64_MPU 0xf0 -/* store qspi ref clock */ +/* + * Bits[31:28] reserved for DM DDR retention, bits[27:0] reserved for SOC 64-bit + * storing qspi ref clock(kHz) + */ #define SYSMGR_SOC64_BOOT_SCRATCH_COLD0 0x200 /* store osc1 clock freq */ #define SYSMGR_SOC64_BOOT_SCRATCH_COLD1 0x204 @@ -85,6 +88,13 @@ void populate_sysmgr_pinmux(void); #define SYSMGR_SOC64_HPS_OSC_CLK 0x1358 #define SYSMGR_SOC64_IODELAY0 0x1400
+/* + * Bits for SYSMGR_SOC64_BOOT_SCRATCH_COLD0 + * Bits[31:28] reserved for DM DDR retention, bits[27:0] reserved for SOC 64-bit + * storing qspi ref clock(kHz) + */ +#define SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK GENMASK(27, 0) + #define SYSMGR_SDMMC SYSMGR_SOC64_SDMMC
#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0) diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-socfpga/mailbox_s10.c index 429444f069..2e43131c5d 100644 --- a/arch/arm/mach-socfpga/mailbox_s10.c +++ b/arch/arm/mach-socfpga/mailbox_s10.c @@ -359,7 +359,7 @@ int mbox_qspi_open(void) { int ret; u32 resp_buf[1]; - u32 resp_buf_len; + u32 resp_buf_len, temp;
ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_QSPI_OPEN, MBOX_CMD_DIRECT, 0, NULL, 0, 0, NULL); @@ -384,8 +384,30 @@ int mbox_qspi_open(void) goto error;
/* We are getting QSPI ref clock and set into sysmgr boot register */ - printf("QSPI: Reference clock at %d Hz\n", resp_buf[0]); - writel(resp_buf[0], + /* + * Only clock freq in kHz degree is accepted due to limited bits[27:0] + * is reserved for storing the QSPI clock freq into boot scratch cold0 + * register + */ + if (resp_buf[0] < 1000) { + ret = -EINVAL; + goto error; + } else { + resp_buf[0] /= 1000; + } + + printf("QSPI: Reference clock at %d kHz\n", resp_buf[0]); + + /* + * DDR retention bit, SHA comparison bit and reset type bits sharing the + * same scratch register in DM, ensure the content inside register is + * not overwritten by QSPI ref clock(kHz) + */ + temp = readl(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_BOOT_SCRATCH_COLD0) & + ~(SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK); + + writel((resp_buf[0] & SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK) | temp, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
return 0;