On 8/30/07, Ben Warren bwarren@qstreams.com wrote:
One other thing I just thought of - you need to make sure the Local Bus Access Windows are set properly. My chip has separate ones for DDR and for Local Bus, and yours may as well. The config file you sent has the LAWBAR for local bus set to 0x000c0000, when it should be 0xf8000000, I think. If this is set wrong, I don't think you'll be able to access the memory range. Info is in the 'System Configuration' section of your reference manual.
Which manual? I tried
This part I'm having problems understanding. This is what I have for the config of MPC8548CDS board - what I'm using as a reference:
; Initialize LAWBAR's WM32 0xe0000C08 0x00000000 ;LAWBAR0 : @0x00000000 WM32 0xe0000C10 0x80f0001b ;LAWAR0 : DDR/SDRAM 256MB WM32 0xe0000C28 0x000c0000 ;LAWBAR1 : @0xc0000000 WM32 0xe0000C30 0x8040001d ;LAWAR1 : Local Bus 1GB
In what manual is this explained in, ie the 0xe0000 addresses? I can't seem to tie together the LAW's in my init.S and the LAW's here.
/* * LAW(Local Access Window) configuration: * * 0x0000_0000 0x7fff_ffff DDR 2G * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M * 0xa000_0000 0xbfff_ffff PCIe MEM 512M * 0xc000_0000 0xdfff_ffff PCI2 MEM 512M * 0xe000_0000 0xe000_ffff CCSR 1M * 0xe200_0000 0xe10f_ffff PCI1 IO 1M * 0xe280_0000 0xe20f_ffff PCI2 IO 1M * 0xe300_0000 0xe30f_ffff PCIe IO 1M * 0xf800_0000 0xffff_ffff FLASH (boot bank) 128M * * Notes: * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. * If flash is 8M at default position (last 8M), no LAW needed. * * LAW 0 is reserved for boot mapping */
.section .bootpg, "ax" .globl law_entry law_entry: entry_start
.long (4f-3f)/6 3: .long 0 .long (LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN
.long (CFG_PCI1_MEM_PHYS>>12) & 0xfffff .long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
.long (CFG_PCI1_IO_PHYS>>12) & 0xfffff .long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M)
.long (CFG_PCI2_MEM_PHYS>>12) & 0xfffff .long LAWAR_EN | LAWAR_TRGT_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)
.long (CFG_PCI2_IO_PHYS>>12) & 0xfffff .long LAWAR_EN | LAWAR_TRGT_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M)
.long (CFG_PCIE1_MEM_PHYS>>12) & 0xfffff .long LAWAR_EN | LAWAR_TRGT_PCIE | (LAWAR_SIZE & LAWAR_SIZE_512M)
.long (CFG_PCIE1_IO_PHYS>>12) & 0xfffff .long LAWAR_EN | LAWAR_TRGT_PCIE | (LAWAR_SIZE & LAWAR_SIZE_1M) 4: entry_end
Fun stuff, eh?
For sure ;-). Robert