This patch adds SD boot support for LS1021ATWR board. SPL framework is used. PBL initialize the internal RAM and copy SPL to it, then SPL initialize DDR using SPD and copy u-boot from SD card to DDR, finally SPL transfer control to u-boot.
Signed-off-by: Alison Wang alison.wang@freescale.com Signed-off-by: Jason Jin jason.jin@freescale.com --- board/freescale/ls1021atwr/ls1021atwr.c | 31 ++++++++++++++++- board/freescale/ls1021atwr/ls102xa_pbi.cfg | 8 +++++ board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg | 14 ++++++++ boards.cfg | 1 + include/configs/ls1021atwr.h | 49 +++++++++++++++++++++++++++ 5 files changed, 102 insertions(+), 1 deletion(-) create mode 100644 board/freescale/ls1021atwr/ls102xa_pbi.cfg create mode 100644 board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index 3de5b83..02d0d39 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -16,6 +16,7 @@ #include <netdev.h> #include <fsl_mdio.h> #include <tsec.h> +#include <spl.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -66,6 +67,7 @@ struct cpld_data { u8 rev2; /* Reserved */ };
+#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT) static void convert_serdes_mux(int type, int need_reset);
void cpld_show(void) @@ -103,11 +105,14 @@ void cpld_show(void) in_8(&cpld_data->serdes_mux)); #endif } +#endif
int checkboard(void) { puts("Board: LS1021ATWR\n"); +#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT) cpld_show(); +#endif
return 0; } @@ -218,6 +223,7 @@ int board_eth_init(bd_t *bis) } #endif
+#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT) int config_serdes_mux(void) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); @@ -249,6 +255,7 @@ int config_serdes_mux(void)
return 0; } +#endif
int board_early_init_f(void) { @@ -273,6 +280,25 @@ int board_early_init_f(void) return 0; }
+#ifdef CONFIG_SPL_BUILD +void board_init_f(ulong dummy) +{ + /* Set global data pointer */ + gd = &gdata; + + /* Clear the BSS */ + memset(__bss_start, 0, __bss_end - __bss_start); + + get_clocks(); + + preloader_console_init(); + + dram_init(); + + board_init_r(NULL, 0); +} +#endif + int board_init(void) { struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; @@ -284,9 +310,10 @@ int board_init(void)
#ifndef CONFIG_SYS_FSL_NO_SERDES fsl_serdes_init(); +#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT) config_serdes_mux(); #endif - +#endif return 0; }
@@ -312,6 +339,7 @@ u16 flash_read16(void *addr) return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); }
+#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT) static void convert_flash_bank(char bank) { struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); @@ -497,3 +525,4 @@ U_BOOT_CMD( " -change lane C & lane D to PCIeX2\n" "\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\n" ); +#endif diff --git a/board/freescale/ls1021atwr/ls102xa_pbi.cfg b/board/freescale/ls1021atwr/ls102xa_pbi.cfg new file mode 100644 index 0000000..edf9f94 --- /dev/null +++ b/board/freescale/ls1021atwr/ls102xa_pbi.cfg @@ -0,0 +1,8 @@ +#PBI commands + +#Configure Scratch register +09ee0200 10000000 +#Configure alternate space +09570158 00080000 +#Flush PBL data +096100c0 000FFFFF diff --git a/board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg b/board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg new file mode 100644 index 0000000..05e2082 --- /dev/null +++ b/board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg @@ -0,0 +1,14 @@ +#PBL preamble and RCW header +aa55aa55 01ee0100 + +#enable IFC, disable QSPI and DSPI +#0608000a 00000000 00000000 00000000 +#20000000 00404000 60025a00 21042000 +#00200000 00000000 00000000 01038000 +#00000000 001b1200 00000000 00000000 + +#disable IFC, enable QSPI and DSPI +0608000a 00000000 00000000 00000000 +20000000 00404000 60025a00 21042000 +00000000 00000000 00000000 01038000 +20024800 001b1200 00000000 00000000 diff --git a/boards.cfg b/boards.cfg index 3e5e1d0..65c3066 100644 --- a/boards.cfg +++ b/boards.cfg @@ -304,6 +304,7 @@ Active arm armv7 keystone ti k2hk_evm Active arm armv7 ls102xa freescale ls1021aqds ls1021aqds_nor ls1021aqds Alison Wang alison.wang@freescale.com Active arm armv7 ls102xa freescale ls1021aqds ls1021aqds_sdcard ls1021aqds:RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT Alison Wang alison.wang@freescale.com Active arm armv7 ls102xa freescale ls1021atwr ls1021atwr_nor ls1021atwr Alison Wang alison.wang@freescale.com +Active arm armv7 ls102xa freescale ls1021atwr ls1021atwr_sdcard ls1021atwr:RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT Alison Wang alison.wang@freescale.com Active arm armv7 mx5 denx m53evk m53evk m53evk:IMX_CONFIG=board/denx/m53evk/imximage.cfg Marek Vasut marek.vasut@gmail.com Active arm armv7 mx5 esg ima3-mx53 ima3-mx53 ima3-mx53:IMX_CONFIG=board/esg/ima3-mx53/imximage.cfg - Active arm armv7 mx5 freescale mx51evk mx51evk mx51evk:IMX_CONFIG=board/freescale/mx51evk/imximage.cfg Stefano Babic sbabic@denx.de diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 5e1f958..806d143 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -43,6 +43,42 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_CLK_FREQ 100000000 #define CONFIG_DDR_CLK_FREQ 100000000
+#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg +#endif + +#ifdef CONFIG_SD_BOOT +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg +#define CONFIG_SPL +#define CONFIG_SPL_PBL_PAD +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/ls102xa/u-boot-spl.lds" +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_WATCHDOG_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x78 +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 + +#define CONFIG_SPL_TEXT_BASE 0x10000000 +#define CONFIG_SPL_MAX_SIZE 0xd000 +#define CONFIG_SPL_STACK 0x1000f000 +#define CONFIG_SPL_PAD_TO 0xe000 +#define CONFIG_SYS_TEXT_BASE 0x82000000 + +#define CONFIG_SYS_SPL_MALLOC_START 0x80200000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 +#define CONFIG_SPL_BSS_START_ADDR 0x80100000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_MONITOR_LEN 0x80000 +#define CONFIG_SYS_SPL_ASSUME_UBOOT_NIH +#define CONFIG_SYS_NO_FLASH +#endif + #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0x67f80000 #endif @@ -59,6 +95,7 @@ unsigned long get_board_ddr_clk(void); /* * IFC Definitions */ +#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT) #define CONFIG_FSL_IFC #define CONFIG_SYS_FLASH_BASE 0x60000000 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE @@ -102,6 +139,7 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+#endif
/* CPLD */
@@ -266,17 +304,28 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif
/* * Environment */ #define CONFIG_ENV_OVERWRITE
+#if defined(CONFIG_SD_BOOT) +#define CONFIG_ENV_OFFSET (1024 * 1024) +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_SIZE 0x20000 +#else #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_SIZE 0x20000 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ +#endif
#define CONFIG_OF_LIBFDT #define CONFIG_OF_BOARD_SETUP