Re: [U-Boot] [PATCH 4/4] Armada100: Enable Ethernet support for GplugD

-----Original Message----- From: Ajay Bhargav [mailto:ajay.bhargav@einfochips.com] Sent: Monday, July 18, 2011 3:12 PM To: Prafulla Wadaskar Cc: u-boot@lists.denx.de; Ajay Bhargav Subject: [PATCH 4/4] Armada100: Enable Ethernet support for GplugD

BTW: This should be third patch, PHY support should be after FEC support.

This patch enables ethernet support for Marvell GplugD board. Network related commands works.

Signed-off-by: Ajay Bhargav ajay.bhargav@einfochips.com

arch/arm/include/asm/arch-armada100/armada100.h | 57 +++++++++++++++++++++++ arch/arm/include/asm/arch-armada100/mfp.h | 19 ++++++++ board/Marvell/gplugd/gplugd.c | 38 +++++++++++++++ include/configs/gplugd.h | 19 +++++++- 4 files changed, 131 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/arch-armada100/armada100.h b/arch/arm/include/asm/arch-armada100/armada100.h index 3d567eb..849638d 100644 --- a/arch/arm/include/asm/arch-armada100/armada100.h +++ b/arch/arm/include/asm/arch-armada100/armada100.h @@ -41,6 +41,10 @@ /* Functional Clock Selection Mask */ #define APBC_FNCLKSEL(x) (((x) & 0xf) << 4)

+/* Fast Ethernet Controller Clock register definition */ +#define FE_CLK_RST 0x1 +#define FE_CLK_ENA 0x8

Modifying armada100.h is not a part of board support patch, pls abstract and put it in separate patch

/* Register Base Addresses */ #define ARMD1_DRAM_BASE 0xB0000000 #define ARMD1_TIMER_BASE 0xD4014000 @@ -85,6 +89,59 @@ struct armd1mpmu_registers { };

/*

• • Application Subsystem Power Management
• • Refer Datasheet Appendix A.9
• */

+struct armd1apmu_registers {

• u32 pcr; /* 0x000 */
• u32 ccr; /* 0x004 */
• u32 pad1;
• u32 ccsr; /* 0x00C */
• u32 fc_timer; /* 0x010 */
• u32 pad2;
• u32 ideal_cfg; /* 0x018 */
• u8 pad3[0x04C - 0x018 - 4];
• u32 lcdcrc; /* 0x04C */
• u32 cciccrc; /* 0x050 */
• u32 sd1crc; /* 0x054 */
• u32 sd2crc; /* 0x058 */
• u32 usbcrc; /* 0x05C */
• u32 nfccrc; /* 0x060 */
• u32 dmacrc; /* 0x064 */
• u32 pad4;
• u32 buscrc; /* 0x06C */
• u8 pad5[0x07C - 0x06C - 4];
• u32 wake_clr; /* 0x07C */
• u8 pad6[0x090 - 0x07C - 4];
• u32 core_status; /* 0x090 */
• u32 rfsc; /* 0x094 */
• u32 imr; /* 0x098 */
• u32 irwc; /* 0x09C */
• u32 isr; /* 0x0A0 */
• u8 pad7[0x0B0 - 0x0A0 - 4];
• u32 mhst; /* 0x0B0 */
• u32 msr; /* 0x0B4 */
• u8 pad8[0x0C0 - 0x0B4 - 4];
• u32 msst; /* 0x0C0 */
• u32 pllss; /* 0x0C4 */
• u32 smb; /* 0x0C8 */
• u32 gccrc; /* 0x0CC */
• u8 pad9[0x0D4 - 0x0CC - 4];
• u32 smccrc; /* 0x0D4 */
• u32 pad10;
• u32 xdcrc; /* 0x0DC */
• u32 sd3crc; /* 0x0E0 */
• u32 sd4crc; /* 0x0E4 */
• u8 pad11[0x0F0 - 0x0E4 - 4];
• u32 cfcrc; /* 0x0F0 */
• u32 mspcrc; /* 0x0F4 */
• u32 cmucrc; /* 0x0F8 */
• u32 fecrc; /* 0x0FC */
• u32 pciecrc; /* 0x100 */
• u32 epdcrc; /* 0x104 */

+};

+/*

• APB1 Clock Reset/Control Registers
• Refer Datasheet Appendix A.10

*/ diff --git a/arch/arm/include/asm/arch-armada100/mfp.h b/arch/arm/include/asm/arch-armada100/mfp.h index d6e0494..da76b58 100644 --- a/arch/arm/include/asm/arch-armada100/mfp.h +++ b/arch/arm/include/asm/arch-armada100/mfp.h @@ -64,6 +64,25 @@ #define MFP105_CI2C_SDA (MFP_REG(0x1a4) | MFP_AF1 | MFP_DRIVE_MEDIUM) #define MFP106_CI2C_SCL (MFP_REG(0x1a8) | MFP_AF1 | MFP_DRIVE_MEDIUM)

+/* Fast Ethernet */ +#define MFP086_ETH_TXCLK (MFP_REG(0x158) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP087_ETH_TXEN (MFP_REG(0x15C) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP088_ETH_TXDQ3 (MFP_REG(0x160) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP089_ETH_TXDQ2 (MFP_REG(0x164) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP090_ETH_TXDQ1 (MFP_REG(0x168) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP091_ETH_TXDQ0 (MFP_REG(0x16C) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP092_ETH_CRS (MFP_REG(0x170) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP093_ETH_COL (MFP_REG(0x174) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP094_ETH_RXCLK (MFP_REG(0x178) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP095_ETH_RXER (MFP_REG(0x17C) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP096_ETH_RXDQ3 (MFP_REG(0x180) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP097_ETH_RXDQ2 (MFP_REG(0x184) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP098_ETH_RXDQ1 (MFP_REG(0x188) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP099_ETH_RXDQ0 (MFP_REG(0x18C) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP100_ETH_MDC (MFP_REG(0x190) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP101_ETH_MDIO (MFP_REG(0x194) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP103_ETH_RXDV (MFP_REG(0x19C) | MFP_AF5 | MFP_DRIVE_MEDIUM)

Ditto, in separate patch

/* More macros can be defined here... */

#define MFP_PIN_MAX 117 diff --git a/board/Marvell/gplugd/gplugd.c b/board/Marvell/gplugd/gplugd.c index 347a689..f446d92 100644 --- a/board/Marvell/gplugd/gplugd.c +++ b/board/Marvell/gplugd/gplugd.c @@ -35,6 +35,11 @@ #include <asm/gpio.h> #include <miiphy.h>

+#ifdef CONFIG_ARMADA100_FEC +#include <net.h> +#include <netdev.h> +#endif /* CONFIG_ARMADA100_FEC */

You can eliminate #ifdef here, that doesn't harm.

DECLARE_GLOBAL_DATA_PTR;

int board_early_init_f(void) @@ -47,6 +52,26 @@ int board_early_init_f(void) /* Enable Console on UART3 */ MFPO8_UART3_TXD, MFPO9_UART3_RXD,

• /* Ethernet PHY Interface */
  

• MFP086_ETH_TXCLK,
  

• MFP087_ETH_TXEN,
  

• MFP088_ETH_TXDQ3,
  

• MFP089_ETH_TXDQ2,
  

• MFP090_ETH_TXDQ1,
  

• MFP091_ETH_TXDQ0,
  

• MFP092_ETH_CRS,
  

• MFP093_ETH_COL,
  

• MFP094_ETH_RXCLK,
  

• MFP095_ETH_RXER,
  

• MFP096_ETH_RXDQ3,
  

• MFP097_ETH_RXDQ2,
  

• MFP098_ETH_RXDQ1,
  

• MFP099_ETH_RXDQ0,
  

• MFP100_ETH_MDC,
  

• MFP101_ETH_MDIO,
  

• MFP103_ETH_RXDV,
  

• MFP_EOC /*End of configuration*/ }; /* configure MFP's */

@@ -69,6 +94,19 @@ int board_init(void) return 0; }

+#ifdef CONFIG_ARMADA100_FEC +int board_eth_init(bd_t *bis) +{

• struct armd1apmu_registers *apmu_regs =

• (struct armd1apmu_registers *) ARMD1_APMU_BASE;
  

• /* Enable clock of ethernet controller */
• writel(FE_CLK_RST | FE_CLK_ENA, &apmu_regs->fecrc);
• return armada100_fec_initialize();

+} +#endif /* CONFIG_ARMADA100_FEC */

#ifdef CONFIG_RESET_PHY_R /* Configure and initialize PHY chip 88E3015 */ void reset_phy(void) diff --git a/include/configs/gplugd.h b/include/configs/gplugd.h index 412c959..aa8fda1 100644 --- a/include/configs/gplugd.h +++ b/include/configs/gplugd.h @@ -62,12 +62,13 @@ #define CONFIG_CMD_I2C #define CONFIG_CMD_AUTOSCRIPT #undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_NFS

/* GPIO Support */ #define CONFIG_ARMADA100_GPIO

+/* Disable DCACHE */ +#define CONFIG_SYS_DCACHE_OFF

/* PHY configuration */ #define CONFIG_MII #define CONFIG_CMD_MII @@ -79,6 +80,20 @@ /* GPIO Configuration for PHY */ #define CONFIG_SYS_GPIO_PHY_RST 104 /* GPIO104 */

+/* Network configuration */ +#define CONFIG_CMD_PING +#define CONFIG_NET_MULTI +#define CONFIG_ARMADA100_FEC

+/* DHCP Support */ +#define CONFIG_CMD_DHCP +#define CONFIG_BOOTP_DHCP_REQUEST_DELAY 50000 +#define CONFIG_BOOTP_SERVERIP

Above inside #ifdef CONFIG_CMD_NET

+/* Default Boot Parameters */ +#define CONFIG_ROOTPATH "/tftpboot" +#define CONFIG_SYS_IMG_NAME "uImage"

/*

• mv-common.h should be defined after CMD configs since it used them
• to enable certain macros

-- 1.7.0.4