I am trying to boot from SOM-RK3399v2 board. Can't get to u-boot shell, but TPL and SPL seems to be working. Booting from uSD or eMMC works. Reading SPI flash it and diff-ing hex dumps shows nothing weird.
SPI image is created with following commands: make clean distclean && make <my custom conf based on rockpro64> && make -j6 tools/mkimage -n rk3399 -T rkspi -d tpl/u-boot-tpl-dtb.bin:spl/u-boot-spl-dtb.bin spl.bin dd if=spl.bin of=spl-out.bin bs=128K conv=sync cat spl-out.bin u-boot-dtb.img > out.bin dd if=out.bin of=out.bin.pad bs=4M conv=sync dd if=out.bin.pad of=/dev/mtdblock0 conv=sync
I have also tried dd-ing spl-out.bin with u-boot.itb or u-boot.img (with 384 kB offset) directly to SPI device - but result is the same. Same results are also with pinebook-pro-rk3399_defconfig.
ls -lh <files> -rw-r--r-- 1 root root 1.2M Jan 9 01:11 out.bin -rw-r--r-- 1 root root 4.0M Jan 9 01:11 out.bin.pad -rw-r--r-- 1 root root 328K Jan 9 01:11 spl.bin -rw-r--r-- 1 root root 384K Jan 9 01:11 spl-out.bin -rw-r--r-- 1 root root 92K Jan 9 01:10 spl/u-boot-spl-dtb.bin -rw-r--r-- 1 root root 70K Jan 9 01:10 tpl/u-boot-tpl-dtb.bin -rw-r--r-- 1 root root 793K Jan 9 01:09 u-boot-dtb.img -rw-r--r-- 1 root root 793K Jan 9 01:09 u-boot.img -rw-r--r-- 1 root root 945K Jan 9 01:09 u-boot.itb
du -h <files> 41K tpl/u-boot-tpl-dtb.bin 65K spl/u-boot-spl-dtb.bin 117K spl.bin 117K spl-out.bin 529K u-boot-dtb.img 529K u-boot.img 585K u-boot.itb 637K out.bin 637K out.bin.pad
grep OFFS .config CONFIG_ENV_OFFSET=0x3F8000 CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 CONFIG_ERR_PTR_OFFSET=0x0 CONFIG_FIT_EXTERNAL_OFFSET=0x0 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET=0x0 # CONFIG_TRANSLATION_OFFSET is not set
Got same results with native build (on arm64) and cross-compile (amd64). UART console shows:
U-Boot TPL 2021.01-rc5-00011-gc8f2a060a1 (Jan 08 2021 - 14:43:26) Channel 0: LPDDR4, 50MHz BW=32 Col=10 Bk=8 CS0 Row=16/15 CS=1 Die BW=16 Size=2048MB Channel 1: LPDDR4, 50MHz BW=32 Col=10 Bk=8 CS0 Row=16/15 CS=1 Die BW=16 Size=2048MB 256B stride lpddr4_set_rate: change freq to 400000000 mhz 0, 1 lpddr4_set_rate: change freq to 800000000 mhz 1, 0 Trying to boot from BOOTROM Returning to boot ROM...
U-Boot SPL 2021.01-rc5-00011-gc8f2a060a1 (Jan 08 2021 - 14:43:26 -0600) Trying to boot from MMC2 mmc_load_image_raw_sector: mmc block read error Trying to boot from SPI <hang>
Booting from SD and trying to write to the SPI flash from u-boot shell: => sf probe SF: Detected w25q128 with page size 256 Bytes, erase size 4 KiB, total 16 MiB => load mmc 1:1 ${kernel_addr_r} u-boot.itb 970832 bytes read in 60 ms (15.4 MiB/s) => sf write $kernel_addr_r 0x60000 ${filesize} device 0 offset 0x60000, size 0xed050 DH@b@N`@`@`@NL`@H@@N`01& 8" Bpteb x6 00 Written: ERROR-110
=> load mmc 1:1 ${kernel_addr_r} u-boot.img 814892 bytes read in 51 ms (15.2 MiB/s) => sf write $kernel_addr_r 0x60000 ${filesize} device 0 offset 0x60000, size 0xc6f2c DH@b@N`@`@`@NL`@H@@N`00 00 @pteb x6 00 Wbitten:EROR -110
=> load mmc 1:1 ${kernel_addr_r} u-boot-dtb.img 814892 bytes read in 51 ms (15.2 MiB/s) => sf write $kernel_addr_r 0x60000 ${filesize} device 0 offset 0x60000, size 0xc6f2c DH@b@N`@`@`@NL`@H@@N`00! 002@qt@s 0p60000 ritten: ERROR -110
If I skip dd-ing u-boot.itb part then UART console shows: dd if=spl.bin of=/dev/mtdblock0 conv=fsync U-Boot TPL 2021.01-rc5-00011-gc8f2a060a1 (Jan 09 2021 - 16:43:10) Channel 0: LPDDR4, 50MHz BW=32 Col=10 Bk=8 CS0 Row=16/15 CS=1 Die BW=16 Size=2048MB Channel 1: LPDDR4, 50MHz BW=32 Col=10 Bk=8 CS0 Row=16/15 CS=1 Die BW=16 Size=2048MB 256B stride lpddr4_set_rate: change freq to 400000000 mhz 0, 1 lpddr4_set_rate: change freq to 800000000 mhz 1, 0 Trying to boot from BOOTROM Returning to boot ROM...
U-Boot SPL 2021.01-rc5-00011-gc8f2a060a1 (Jan 09 2021 - 16:43:10 +0100) Trying to boot from MMC2 mmc_load_image_raw_sector: mmc block read error Trying to boot from SPI Trying to boot from MMC1 mmc_load_image_raw_sector: mmc block read error SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ###
Booting from SPI flash with extra logs: grep _LOG_ .config CONFIG_LOG_MAX_LEVEL=7 CONFIG_LOG_DEFAULT_LEVEL=7 CONFIG_LOG_CONSOLE=y # CONFIG_LOG_SYSLOG is not set CONFIG_SPL_LOG_MAX_LEVEL=7 CONFIG_SPL_LOG_CONSOLE=y CONFIG_TPL_LOG_MAX_LEVEL=7 CONFIG_TPL_LOG_CONSOLE=y # CONFIG_LOG_ERROR_RETURN is not set
UART console: common/spl/spl.c:601-board_init_r() >>TPL: board_init_r() common/spl/spl.c:601-board_init_r() >>TPL: board_init_r() common/spl/spl.c:601-board_init_r() >>TPL: board_init_r() common/spl/spl.c:601-board_init_r() >>TPL: board_init_r() <repeats for minutes...>