the virtex2 fpga download code watches for init going active during a download of config data as an error condition. init also goes active after a configuration is finished in concert with the done signal. The code in cvs doesn't check for done active until all of the configuration data is sent.
On our board the done signal would go active "early" as the configuration data has a few extra pad bytes at the end, but the code would print an error message even though the download had suceeded.
The patch adds a check for done going active before checking init. If done is seen active the byte loading is cut short. If debugging is on it will print the count where it finished (8 bytes early for us). It also changes the printf string to indicate the counts it prints are in ticks and not mS.
I only have a system with 'slave parallel' style config interface, so I've only patched that download version. The virtex2 slave serial and spartan2 versions may have the same problem, I didn't have time to look.