Re: [U-Boot] [PATCH 7/7] MSCC: Add board support for Jaguar2 SOC family.

Am 06.01.19 um 18:23 schrieb Horatiu Vultur:

Add board support for Jaguar2 SOC family. The detection of the board type in this family is based on the phy ids.

Signed-off-by: Horatiu Vultur horatiu.vultur@microchip.com

arch/mips/mach-mscc/Makefile | 5 +- board/mscc/common/spi.c | 31 ++++++++++ board/mscc/jr2/Kconfig | 15 +++++ board/mscc/{ocelot => jr2}/Makefile | 2 +- board/mscc/jr2/jr2.c | 117 ++++++++++++++++++++++++++++++++++++ board/mscc/ocelot/Makefile | 2 +- board/mscc/ocelot/ocelot.c | 22 ------- 7 files changed, 168 insertions(+), 26 deletions(-) create mode 100644 board/mscc/common/spi.c create mode 100644 board/mscc/jr2/Kconfig copy board/mscc/{ocelot => jr2}/Makefile (50%) create mode 100644 board/mscc/jr2/jr2.c

diff --git a/arch/mips/mach-mscc/Makefile b/arch/mips/mach-mscc/Makefile index 44538b7..f5b6968 100644 --- a/arch/mips/mach-mscc/Makefile +++ b/arch/mips/mach-mscc/Makefile @@ -2,5 +2,6 @@

CFLAGS_cpu.o += -finline-limit=64000

-obj-y += cpu.o dram.o reset.o phy.o gpio.o lowlevel_init.o -obj-$(CONFIG_SOC_LUTON) += lowlevel_init_luton.o +obj-y += cpu.o dram.o reset.o phy.o lowlevel_init.o +obj-$(CONFIG_SOC_LUTON) += lowlevel_init_luton.o gpio.o +obj-$(CONFIG_SOC_OCELOT) += gpio.o diff --git a/board/mscc/common/spi.c b/board/mscc/common/spi.c new file mode 100644 index 0000000..0566fcb --- /dev/null +++ b/board/mscc/common/spi.c @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/*

• • Copyright (c) 2018 Microsemi Coprporation
• */

+#include <common.h> +#include <asm/io.h> +#include <spi.h>

+void external_cs_manage(struct udevice *dev, bool enable) +{

• u32 cs = spi_chip_select(dev);
• /* IF_SI0_OWNER, select the owner of the SI interface

• * Encoding: 0: SI Slave
  

• *	     1: SI Boot Master
  

• *	     2: SI Master Controller
  

• */
  

• if (!enable) {

• writel(ICPU_SW_MODE_SW_PIN_CTRL_MODE |
  

•        ICPU_SW_MODE_SW_SPI_CS(BIT(cs)),
  

•        BASE_CFG + ICPU_SW_MODE);
  

• clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
  

• 		ICPU_GENERAL_CTRL_IF_SI_OWNER_M,
  

• 		ICPU_GENERAL_CTRL_IF_SI_OWNER(2));
  

• } else {

• writel(0, BASE_CFG + ICPU_SW_MODE);
  

• clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
  

• 		ICPU_GENERAL_CTRL_IF_SI_OWNER_M,
  

• 		ICPU_GENERAL_CTRL_IF_SI_OWNER(1));
  

• }

+} diff --git a/board/mscc/jr2/Kconfig b/board/mscc/jr2/Kconfig new file mode 100644 index 0000000..68a2de8 --- /dev/null +++ b/board/mscc/jr2/Kconfig @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: (GPL-2.0+ OR MIT)

+config SYS_VENDOR

• default "mscc"

+if SOC_JR2

+config SYS_BOARD

• default "jr2"

+config SYS_CONFIG_NAME

• default "jr2"

+endif

diff --git a/board/mscc/ocelot/Makefile b/board/mscc/jr2/Makefile similarity index 50% copy from board/mscc/ocelot/Makefile copy to board/mscc/jr2/Makefile index 9f28c81..2b5c1c7 100644 --- a/board/mscc/ocelot/Makefile +++ b/board/mscc/jr2/Makefile @@ -1,4 +1,4 @@ # SPDX-License-Identifier: (GPL-2.0+ OR MIT)

-obj-$(CONFIG_SOC_OCELOT) := ocelot.o +obj-$(CONFIG_SOC_JR2) := jr2.o ../common/spi.o

if you add board/mscc/common/Makefile, Kbuild will automatically build and link the common code for each board. Thus manually pulling common code is not necessary.

diff --git a/board/mscc/jr2/jr2.c b/board/mscc/jr2/jr2.c new file mode 100644 index 0000000..36f9896 --- /dev/null +++ b/board/mscc/jr2/jr2.c @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/*

• • Copyright (c) 2018 Microsemi Corporation
• */

+#include <common.h> +#include <asm/io.h> +#include <led.h>

+DECLARE_GLOBAL_DATA_PTR;

+enum {

• BOARD_TYPE_PCB110 = 0xAABBCE00,
• BOARD_TYPE_PCB111,
• BOARD_TYPE_PCB112,

+};

+int board_early_init_r(void) +{

• /* Prepare SPI controller to be used in master mode */
• writel(0, BASE_CFG + ICPU_SW_MODE);
• clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,

• 	ICPU_GENERAL_CTRL_IF_SI_OWNER_M,
  

• 	ICPU_GENERAL_CTRL_IF_SI_OWNER(2));
  

• /* Address of boot parameters */
• gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
• /* LED setup */
• if (IS_ENABLED(CONFIG_LED))

• led_default_state();
  

• return 0;

+}

+static void vcoreiii_gpio_set_alternate(int gpio, int mode) +{

• u32 mask;
• u32 val0, val1;
• void __iomem *reg0, *reg1;
• if (gpio < 32) {

• mask = BIT(gpio);
  

• reg0 = BASE_CFG + GPIO_GPIO_ALT(0);
  

• reg1 = BASE_CFG + GPIO_GPIO_ALT(1);
  

• } else {

• gpio -= 32;
  

• mask = BIT(gpio);
  

• reg0 = BASE_CFG + GPIO_GPIO_ALT1(0);
  

• reg1 = BASE_CFG + GPIO_GPIO_ALT1(1);
  

• }
• val0 = readl(reg0);
• val1 = readl(reg1);
• if (mode == 1) {

• writel(val0 | mask, reg0);
  

• writel(val1 & ~mask, reg1);
  

• } else if (mode == 2) {

• writel(val0 & ~mask, reg0);
  

• writel(val1 | mask, reg1);
  

• } else if (mode == 3) {

• writel(val0 | mask, reg0);
  

• writel(val1 | mask, reg1);
  

• } else {

• writel(val0 & ~mask, reg0);
  

• writel(val1 & ~mask, reg1);
  

• }

+}

+static void do_board_detect(void) +{

• int i;
• u16 pval;
• /* MIIM 1 + 2 MDC/MDIO */
• for (i = 56; i < 60; i++)

• vcoreiii_gpio_set_alternate(i, 1);
  

• if (mscc_phy_rd(0, 0x10, 0x3, &pval) == 0 &&

•    ((pval >> 4) & 0x3F) == 0x3c) {
  

• gd->board_type = BOARD_TYPE_PCB112; /* Serval2-NID */
  

• } else if (mscc_phy_rd(1, 0x0, 0x3, &pval) == 0 &&

•    ((pval >> 4) & 0x3F) == 0x3c) {
  

• gd->board_type = BOARD_TYPE_PCB110; /* Jr2-24 */
  

• } else {

• /* Fall-back */
  

• gd->board_type = BOARD_TYPE_PCB111; /* Jr2-48 */
  

• }

+}

+#if defined(CONFIG_MULTI_DTB_FIT) +int board_fit_config_name_match(const char *name) +{

• if (gd->board_type == BOARD_TYPE_PCB110 &&

•    strcmp(name, "jr2_pcb110") == 0)
  

• return 0;
  

• if (gd->board_type == BOARD_TYPE_PCB111 &&

•    strcmp(name, "jr2_pcb111") == 0)
  

• return 0;
  

• if (gd->board_type == BOARD_TYPE_PCB112 &&

•    strcmp(name, "serval2_pcb112") == 0)
  

• return 0;
  

• return -1;

+} +#endif

+#if defined(CONFIG_DTB_RESELECT) +int embedded_dtb_select(void) +{

• do_board_detect();
• fdtdec_setup();
• return 0;

+} +#endif diff --git a/board/mscc/ocelot/Makefile b/board/mscc/ocelot/Makefile index 9f28c81..54e6a06 100644 --- a/board/mscc/ocelot/Makefile +++ b/board/mscc/ocelot/Makefile @@ -1,4 +1,4 @@ # SPDX-License-Identifier: (GPL-2.0+ OR MIT)

-obj-$(CONFIG_SOC_OCELOT) := ocelot.o +obj-$(CONFIG_SOC_OCELOT) := ocelot.o ../common/spi.o

diff --git a/board/mscc/ocelot/ocelot.c b/board/mscc/ocelot/ocelot.c index a05c308..0f7a532 100644 --- a/board/mscc/ocelot/ocelot.c +++ b/board/mscc/ocelot/ocelot.c @@ -18,28 +18,6 @@ enum { BOARD_TYPE_PCB123, };

-void external_cs_manage(struct udevice *dev, bool enable) -{

• u32 cs = spi_chip_select(dev);
• /* IF_SI0_OWNER, select the owner of the SI interface

• * Encoding: 0: SI Slave
  

• *	     1: SI Boot Master
  

• *	     2: SI Master Controller
  

• */
  

• if (!enable) {

• writel(ICPU_SW_MODE_SW_PIN_CTRL_MODE |
  

•        ICPU_SW_MODE_SW_SPI_CS(BIT(cs)), BASE_CFG + ICPU_SW_MODE);
  

• clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
  

• 		ICPU_GENERAL_CTRL_IF_SI_OWNER_M,
  

• 		ICPU_GENERAL_CTRL_IF_SI_OWNER(2));
  

• } else {

• writel(0, BASE_CFG + ICPU_SW_MODE);
  

• clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
  

• 		ICPU_GENERAL_CTRL_IF_SI_OWNER_M,
  

• 		ICPU_GENERAL_CTRL_IF_SI_OWNER(1));
  

• }

-}

void board_debug_uart_init(void) { /* too early for the pinctrl driver, so configure the UART pins here */