On 3/26/21 10:18 PM, Green Wan wrote:
Clear feature disable CSR to turn on all features of hart. The detail is specified at section, 'SiFive Feature Disable CSR', in user manual
https://sifive.cdn.prismic.io/sifive/aee0dd4c-d156-496e-a6c4-db0cf54bbe68_si...
Signed-off-by: Green Wan green.wan@sifive.com
board/sifive/unmatched/spl.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)
diff --git a/board/sifive/unmatched/spl.c b/board/sifive/unmatched/spl.c index 5e1333b09a..e3f3d82df4 100644 --- a/board/sifive/unmatched/spl.c +++ b/board/sifive/unmatched/spl.c @@ -12,6 +12,7 @@ #include <log.h> #include <linux/delay.h> #include <linux/io.h> +#include <asm/csr.h> #include <asm/gpio.h> #include <asm/arch/gpio.h> #include <asm/arch/spl.h> @@ -22,6 +23,21 @@ #define MODE_SELECT_SD 0xb #define MODE_SELECT_MASK GENMASK(3, 0)
+#define CSR_U74_FEATURE_DISABLE 0x7c1
+void riscv_hart_early_init(void) +{
- /*
* Feature Disable CSR** Clear feature disable CSR to '0' to turn on all features for* each core. This operation must be in m-mode.*/- if (CONFIG_IS_ENABLED(RISCV_MMODE)) {
csr_write(CSR_U74_FEATURE_DISABLE, 0);- }
These braces are not strictly necessary.
+}
- int spl_board_init_f(void) { int ret;
Reviewed-by: Sean Anderson seanga2@gmail.com