[ Linux commit 9afbe7c0140f663586edb6e823b616bd7076c00a ]
If the write protect signal from this IP is connected to the NAND device, this IP can handle the WP# pin via the WRITE_PROTECT register.
The Denali NAND Flash Memory Controller User's Guide describes this register like follows:
When the controller is in reset, the WP# pin is always asserted to the device. Once the reset is removed, the WP# is de-asserted. The software will then have to come and program this bit to assert/de-assert the same.
1 - Write protect de-assert 0 - Write protect assert
The default value is 1, so the write protect is de-asserted after the reset is removed. The driver can write to the device unless someone has explicitly cleared register before booting the kernel.
The boot ROM of some UniPhier SoCs (LD4, Pro4, sLD8, Pro5) is the case; the boot ROM clears the WRITE_PROTECT register when the system is booting from the NAND device, so the NAND device becomes read-only.
Set it to 1 in the driver in order to allow the write access to the device.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com Signed-off-by: Miquel Raynal miquel.raynal@bootlin.com ---
drivers/mtd/nand/raw/denali.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/mtd/nand/raw/denali.c b/drivers/mtd/nand/raw/denali.c index b525b1be54..f00f6c39e1 100644 --- a/drivers/mtd/nand/raw/denali.c +++ b/drivers/mtd/nand/raw/denali.c @@ -1089,6 +1089,7 @@ static void denali_hw_init(struct denali_nand_info *denali) iowrite32(CHIP_EN_DONT_CARE__FLAG, denali->reg + CHIP_ENABLE_DONT_CARE);
iowrite32(0xffff, denali->reg + SPARE_AREA_MARKER); + iowrite32(WRITE_PROTECT__FLAG, denali->reg + WRITE_PROTECT); }
int denali_calc_ecc_bytes(int step_size, int strength)