From 3ce16a34751437f67b349e5aaff0fcc9f1620f1a Mon Sep 17 00:00:00 2001
From: Syed Mohammed Khasim khasim@ti.com Date: Sat, 9 Jan 2010 09:31:15 +0530 Subject: [PATCH] Add support for 720Mhz
A New API to allow setting M value to support 720Mhz
Signed-off-by: Syed Mohammed Khasim khasim@ti.com --- cpu/arm_cortexa8/omap3/clock.c | 21 +++++++++++++++++++++ 1 files changed, 21 insertions(+), 0 deletions(-)
diff --git a/cpu/arm_cortexa8/omap3/clock.c b/cpu/arm_cortexa8/omap3/clock.c index 174c453..d67517a 100644 --- a/cpu/arm_cortexa8/omap3/clock.c +++ b/cpu/arm_cortexa8/omap3/clock.c @@ -402,3 +402,24 @@ void per_clocks_enable(void)
sdelay(1000); } + +/* + * Configure PRCM registers to get 720 Mhz + * + * NOTE: N value doesn't change, only M gets affected + */ +void prcm_config_720mhz(void) +{ + struct prcm *prcm_base = (struct prcm *)PRCM_BASE; + + /* Unlock MPU DPLL (slows things down, and needed later) */ + sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOW_POWER_BYPASS); + wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu, LDELAY); + + /* Set M */ + sr32(&prcm_base->clksel1_pll_mpu, 8, 11, 0x2D0); + + /* lock mode */ + sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOCK); + wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu, LDELAY); +}