On 04/08/14 08:42, Tim Harvey wrote:
On Sun, Aug 3, 2014 at 12:34 AM, Nikita Kiryanov nikita@compulab.co.il wrote:
According to MX6 TRM, both MMDC and DRAM should be configured to the same powerdown precharge. Currently, mx6_dram_cfg() configures MMDC for fast pd, and the DRAM for slow pd.
Nikita,
I'm inclined to agree with you. A glance at some of the existing non-spl board config's show this same discrepancy which probably comes form an error in the IMX DDR3 Script Aid spreadsheet (https://community.freescale.com/docs/DOC-94917).
I would at least add to the description the fact that the precharge pd is MR0 bit12 for DRAM and the current value of 0 indicates 'Slow exit (DLL off)'. I've asked our Freescale FAE for clarification to see if the spreadsheet is in error.
OK, I'll add it once the FAE confirms the error.
Regards,
Tim