Hi Andreas,
-----Original Message----- From: Andreas Bießmann [mailto:andreas.devel@googlemail.com] Sent: 2016年1月25日 5:42 To: Wu, Josh Josh.wu@atmel.com; Scott Wood scottwood@freescale.com; U-Boot Mailing List u-boot@lists.denx.de Cc: Yang, Wenyou Wenyou.Yang@atmel.com; Bo Shen voice.shen@gmail.com Subject: Re: [PATCH 3/4] atmel_nand: increase more delay to support MT29F32G08CBADA
Hi Josh,
On 24.11.15 09:26, Josh Wu wrote:
The tR is 100us in the datasheet section: Array Characteristics
I've seen 50us for tR. Which datasheet do you have?
The datasheet is downloaded from micron official website.
https://www.micron.com/parts/nand-flash/mass-storage/mt29f32g08cbadawp?pc=%7...
This device requires the number of bits ECC correctability is 40 bits,
but the maximum error correction capability of PMECC IP of SAMA5D2 is 32 bits.
That is, SAMA5D2 can't support this device.
So, I suggest to drop this patch.
Andreas
Signed-off-by: Josh Wu josh.wu@atmel.com
drivers/mtd/nand/atmel_nand.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c index 5226acf..266dfd9 100644 --- a/drivers/mtd/nand/atmel_nand.c +++ b/drivers/mtd/nand/atmel_nand.c @@ -1492,7 +1492,7 @@ int atmel_nand_chip_init(int devnum, ulong base_addr) #ifdef CONFIG_SYS_NAND_READY_PIN nand->dev_ready = at91_nand_ready; #endif
- nand->chip_delay = 75;
- nand->chip_delay = 100;
#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT nand->bbt_options |= NAND_BBT_USE_FLASH; #endif
Best Regards, Wenyou Yang