T1040 and T1020 are two Freescale SoCs with an integrated VSC9953 Gigabit L2 Switch. This patch initializes this L2 switch on boards with T1040 and T1020.
Signed-off-by: Codrin Ciubotariu codrin.ciubotariu@freescale.com ---
Changes for v2: - added patch description;
Changes for v3: - Removed "Change-id" line from comment;
arch/powerpc/cpu/mpc8xxx/cpu.c | 5 +++++ arch/powerpc/include/asm/config_mpc85xx.h | 3 +++ 2 files changed, 8 insertions(+)
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index 2d28eb2..c92589f 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -15,6 +15,7 @@ #include <netdev.h> #include <asm/cache.h> #include <asm/io.h> +#include <vsc9953.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -271,5 +272,9 @@ int cpu_eth_init(bd_t *bis) #ifdef CONFIG_FMAN_ENET fm_standard_init(bis); #endif + +#ifdef CONFIG_VSC9953 + vsc9953_init(bis); +#endif return 0; } diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 01b0905..79caac1 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -747,6 +747,9 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ +#if defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1020) +#define CONFIG_VSC9953 /* Vitesse L2 Switch */ +#endif #ifdef CONFIG_SYS_FSL_DDR4 #define CONFIG_SYS_FSL_DDRC_GEN4 #endif