On 10/11/2020 08:50, Jaehoon Chung wrote:
EMMC_CFG register has a cfg_ddr bit(BIT[2]). It needs to set when mmc is running to ddr mode. Otherwise, its bit should be cleared. CFG_DDR[2] - 1: DDR mode, 0: SDR mode
Signed-off-by: Jaehoon Chung jh80.chung@samsung.com
arch/arm/include/asm/arch-meson/sd_emmc.h | 1 + drivers/mmc/meson_gx_mmc.c | 5 +++++ 2 files changed, 6 insertions(+)
diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h index 1e9f8cf498b4..c2f77c7308ec 100644 --- a/arch/arm/include/asm/arch-meson/sd_emmc.h +++ b/arch/arm/include/asm/arch-meson/sd_emmc.h @@ -38,6 +38,7 @@ #define CFG_BUS_WIDTH_1 0 #define CFG_BUS_WIDTH_4 1 #define CFG_BUS_WIDTH_8 2 +#define CFG_DDR_MODE BIT(2) #define CFG_BL_LEN_MASK GENMASK(7, 4) #define CFG_BL_LEN_SHIFT 4 #define CFG_BL_LEN_512 (9 << 4) diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c index 7c60e0566560..6fcf6c2ced27 100644 --- a/drivers/mmc/meson_gx_mmc.c +++ b/drivers/mmc/meson_gx_mmc.c @@ -90,6 +90,11 @@ static int meson_dm_mmc_set_ios(struct udevice *dev) else return -EINVAL;
- if (mmc->ddr_mode)
meson_mmc_cfg |= CFG_DDR_MODE;- else
meson_mmc_cfg &= ~CFG_DDR_MODE;- /* 512 bytes block length */ meson_mmc_cfg &= ~CFG_BL_LEN_MASK; meson_mmc_cfg |= CFG_BL_LEN_512;
Interesting, how did it work without this bit ?
This driver seems to really be in a bad state...
Neil