Re: [U-Boot] [PATCH] PPC4xx: PLB4 Arbiter and Memory Queue Optimizations

On Monday 11 August 2008, Prodyut Hazarika wrote:

PLB4 Crossbar Arbiter core is instantiated on 405EX/ 440EP/ 440EPx/ 440GR/ 440GRx/ 440SP/ 440SPe/ 460EX/ 460GT For optimal performance, the read pipeline depth must be set to 4. The current code enables it only for bamboo, sequoia and yosemite boards.

That's not correct. Other non-AMCC 440EP/EPx boards have it set too.

Better approach is to define CONFIG_PLB4_CROSSBAR_ARBITER_CORE for the above PPC4xx families, and to remove the duplicated code from board specfic files.

OK. But on which 4xx boards did you test this change? And could you please remove the duplicated code from the "other", non-AMCC boards too with your next patch version (DU440, PMC440, korat, lwmon5, pcs440ep). I added the other board maintainers to CC.

Also, added register definitions for MemoryQueue related registers, and enabled Memory Queue optimizatios for 460EX/GT.

Signed-off-by: Prodyut Hazarika phazarika@amcc.com

This patch doesn't apply:

[stefan@kubuntu u-boot-ppc4xx (master)]$ git-am -3 patches_amcc/[PATCH]\ PPC4xx:\ PLB4\ Arbiter\ and\ Memory\ Queue\ Optimizations.mbox Applying PPC4xx: PLB4 Arbiter and Memory Queue Optimizations .dotest/patch:125: trailing whitespace.

.dotest/patch:132: trailing whitespace. mtdcr(SDRAM_CONF1HB, val); .dotest/patch:135: trailing whitespace. mtdcr(SDRAM_CONF1LL, val); .dotest/patch:138: trailing whitespace. mtdcr(SDRAM_CONFPATHB, val); .dotest/patch:154: trailing whitespace. mtdcr(plb0_acr, plb0_acr_ppm_fair | fatal: corrupt patch at line 387 Patch failed at 0001. When you have resolved this problem run "git-am -3 --resolved". If you would prefer to skip this patch, instead run "git-am -3 --skip".

There are several whitespace problems which should be fixed too. But the main problem is that the patch doesn't apply at all. How did you generate this patch? I strongly encourage you to use the git tools to handle patches (git-format-patch and git-send-email).

Please find some review comments below.

---

board/amcc/bamboo/bamboo.c | 17 ----------- board/amcc/sequoia/sequoia.c | 17 ----------- board/amcc/yosemite/yosemite.c | 17 ----------- cpu/ppc4xx/44x_spd_ddr2.c | 34 ++++++++++++++++------ cpu/ppc4xx/cpu_init.c | 15 ++++++++++ include/asm-ppc/ppc4xx-sdram.h | 16 ++++++++++ include/ppc440.h | 49 +-------------------------------- include/ppc4xx.h | 60 ++++++++++++++++++++++++++++++++++++++++ 8 files changed, 116 insertions(+), 109 deletions(-)

diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c index f415701..761e418 100644 --- a/board/amcc/bamboo/bamboo.c +++ b/board/amcc/bamboo/bamboo.c @@ -500,23 +500,6 @@ int pci_pre_init(struct pci_controller *hose) addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ mtdcr(plb4_acr, addr);

• /*-----------------------------------------------------------------------

--+ - | Set Nebula PLB4 arbiter to fair mode.

+-------------------------------------------------------------------------* / - /* Segment0 */

• addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
• addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
• addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
• addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
• mtdcr(plb0_acr, addr);
• /* Segment1 */
• addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
• addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
• addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
• addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
• mtdcr(plb1_acr, addr);
• return 1;

} #endif /* defined(CONFIG_PCI) */ diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c index b833092..639db09 100644 --- a/board/amcc/sequoia/sequoia.c +++ b/board/amcc/sequoia/sequoia.c @@ -372,23 +372,6 @@ int pci_pre_init(struct pci_controller *hose) addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ mtdcr(plb4_acr, addr);

• /*

• * Set Nebula PLB4 arbiter to fair mode.
  

• */
  

• /* Segment0 */
• addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
• addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
• addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
• addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
• mtdcr(plb0_acr, addr);
• /* Segment1 */
• addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
• addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
• addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
• addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
• mtdcr(plb1_acr, addr);

#ifdef CONFIG_PCI_PNP hose->fixup_irq = sequoia_pci_fixup_irq; #endif diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c index 05be40a..b18637d 100644 --- a/board/amcc/yosemite/yosemite.c +++ b/board/amcc/yosemite/yosemite.c @@ -366,23 +366,6 @@ int pci_pre_init(struct pci_controller *hose) addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ mtdcr(plb4_acr, addr);

• /*-----------------------------------------------------------------------

--+ - | Set Nebula PLB4 arbiter to fair mode.

+-------------------------------------------------------------------------* / - /* Segment0 */

• addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
• addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
• addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
• addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
• mtdcr(plb0_acr, addr);
• /* Segment1 */
• addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
• addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
• addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
• addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
• mtdcr(plb1_acr, addr);
• return 1;

} #endif /* defined(CONFIG_PCI) */ diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c index e9940e8..042ad1f 100644 --- a/cpu/ppc4xx/44x_spd_ddr2.c +++ b/cpu/ppc4xx/44x_spd_ddr2.c @@ -2241,16 +2241,30 @@ static void program_memory_queue(unsigned long *dimm_populated, }

#if defined(CONFIG_460EX) || defined(CONFIG_460GT)

• /*

• * Enable high bandwidth access on 460EX/GT.
  

• * This should/could probably be done on other
  

• * PPC's too, like 440SPe.
  

• * This is currently not used, but with this setup
  

• * it is possible to use it later on in e.g. the Linux
  

• * EMAC driver for performance gain.
  

• */
  

• mtdcr(SDRAM_PLBADDULL, 0x00000000); /* MQ0_BAUL */
• mtdcr(SDRAM_PLBADDUHB, 0x00000008); /* MQ0_BAUH */

• {

I don't particularly like this extra "{" level without need. Please remove it.

• /*
  

• * Enable high bandwidth access on 460EX/GT.
  

• * This should/could probably be done on other
  

• * PPC's too, like 440SPe.
  

• * This is currently not used, but with this setup
  

• * it is possible to use it later on in e.g. the Linux
  

• * EMAC driver for performance gain.
  

• */
  

Indentation is not correct. Should be:

• /*
  

•  * Enable high bandwidth access on 460EX/GT.
  

...

• unsigned long val;
  

• mtdcr(SDRAM_PLBADDULL, 0x00000000); /* MQ0_BAUL */
  

• mtdcr(SDRAM_PLBADDUHB, 0x00000008); /* MQ0_BAUH */
  

• val = (mfdcr(SDRAM_CONF1HB) | SDRAM_CONF1HB_AAFR | SDRAM_CONF1HB_RPEN |
  

SDRAM_CONF1HB_RFTE); + mtdcr(SDRAM_CONF1HB, val);

Please wrap those too long lines.

• val = (mfdcr(SDRAM_CONF1LL) | SDRAM_CONF1LL_AAFR | SDRAM_CONF1LL_RPEN |
  

SDRAM_CONF1LL_RFTE); + mtdcr(SDRAM_CONF1LL, val);

• val = (mfdcr(SDRAM_CONFPATHB) | SDRAM_CONFPATHB_TPEN);
  

• mtdcr(SDRAM_CONFPATHB, val);
  

• }

#endif }

diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c index ac64279..f7c9200 100644 --- a/cpu/ppc4xx/cpu_init.c +++ b/cpu/ppc4xx/cpu_init.c @@ -288,6 +288,21 @@ cpu_init_f (void) val |= 0x400; mtsdr(SDR0_USB2HOST_CFG, val); #endif /* CONFIG_460EX */

+#ifdef CONFIG_PLB4_CROSSBAR_ARBITER_CORE

• /* Segment0 */
• mtdcr(plb0_acr, plb0_acr_ppm_fair |

• 	plb0_acr_hbu_enabled |
  

• 	plb0_acr_rdp_4deep   |
  

• 	plb0_acr_wrp_2deep);
  

• /* Segment1 */
• mtdcr(plb1_acr, plb1_acr_ppm_fair |

• 	plb1_acr_hbu_enabled |
  

• 	plb1_acr_rdp_4deep   |
  

• 	plb1_acr_wrp_2deep);
  

+#endif

How about 440EPx/GRx and it's problem with the PLB4A0_ACR[WRP]. Currently this gets cleared in a board specific file because of the MAL burst problems in Linux when its set. Shouldn't we configure it correctly in this place for all 440EPx/GRx and remove it from the board specific code?

Please remove this unnecessary empty line.

}

/* diff --git a/include/asm-ppc/ppc4xx-sdram.h b/include/asm-ppc/ppc4xx-sdram.h index e151f0c..1abff94 100644 --- a/include/asm-ppc/ppc4xx-sdram.h +++ b/include/asm-ppc/ppc4xx-sdram.h @@ -266,15 +266,31 @@ #define SDRAM_R2BAS (SDRAMQ_DCR_BASE+0x2) /* rank 2 base address & size */ #define SDRAM_R3BAS (SDRAMQ_DCR_BASE+0x3) /* rank 3 base address & size */ #define SDRAM_CONF1HB (SDRAMQ_DCR_BASE+0x5) /* configuration 1 HB */ +#define SDRAM_CONF1HB_AAFR 0x80000000 /* Address Ack on First Request - Bit 0 */ +#define SDRAM_CONF1HB_PRPD 0x00080000 /* PLB Read pipeline Disable - Bit 12 */ +#define SDRAM_CONF1HB_PWPD 0x00040000 /* PLB Write pipeline Disable - Bit 13 */ +#define SDRAM_CONF1HB_PRW 0x00020000 /* PLB Read Wait - Bit 14 */ +#define SDRAM_CONF1HB_RPEN 0x00000800 /* Read Passing Enable - Bit 20 */ +#define SDRAM_CONF1HB_RFTE 0x00000400 /* Read Flow Through Enable - Bit 21 */ + #define SDRAM_ERRSTATHB (SDRAMQ_DCR_BASE+0x7) /* error status HB */ #define SDRAM_ERRADDUHB (SDRAMQ_DCR_BASE+0x8) /* error address upper 32 HB */ #define SDRAM_ERRADDLHB (SDRAMQ_DCR_BASE+0x9) /* error address lower 32 HB */ #define SDRAM_PLBADDULL (SDRAMQ_DCR_BASE+0xA) /* PLB base address upper 32 LL */ #define SDRAM_CONF1LL (SDRAMQ_DCR_BASE+0xB) /* configuration 1 LL */ +#define SDRAM_CONF1LL_AAFR 0x80000000 /* Address Ack on First Request - Bit 0 */ +#define SDRAM_CONF1LL_PRPD 0x00080000 /* PLB Read pipeline Disable - Bit 12 */ +#define SDRAM_CONF1LL_PWPD 0x00040000 /* PLB Write pipeline Disable - Bit 13 */ +#define SDRAM_CONF1LL_PRW 0x00020000 /* PLB Read Wait - Bit 14 */ +#define SDRAM_CONF1LL_RPEN 0x00000800 /* Read Passing Enable - Bit 20 */ +#define SDRAM_CONF1LL_RFTE 0x00000400 /* Read Flow Through Enable - Bit 21 */ + #define SDRAM_ERRSTATLL (SDRAMQ_DCR_BASE+0xC) /* error status LL */ #define SDRAM_ERRADDULL (SDRAMQ_DCR_BASE+0xD) /* error address upper 32 LL */ #define SDRAM_ERRADDLLL (SDRAMQ_DCR_BASE+0xE) /* error address lower 32 LL */ #define SDRAM_CONFPATHB (SDRAMQ_DCR_BASE+0xF) /* configuration between paths */ +#define SDRAM_CONFPATHB_TPEN 0x08000000 /* Transaction Passing Enable - Bit 4 */ + #define SDRAM_PLBADDUHB (SDRAMQ_DCR_BASE+0x10) /* PLB base address upper 32 LL */

#if !defined(CONFIG_405EX) diff --git a/include/ppc440.h b/include/ppc440.h index c581f1b..8d3a7e3 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -422,53 +422,6 @@

#define PLB4_ACR_WRP (0x80000000 >> 7)

-/* Nebula PLB4 Arbiter - PowerPC440EP */ -#define PLB_ARBITER_BASE 0x80

-#define plb0_revid (PLB_ARBITER_BASE+ 0x00) -#define plb0_acr (PLB_ARBITER_BASE+ 0x01) -#define plb0_acr_ppm_mask 0xF0000000 -#define plb0_acr_ppm_fixed 0x00000000 -#define plb0_acr_ppm_fair 0xD0000000 -#define plb0_acr_hbu_mask 0x08000000 -#define plb0_acr_hbu_disabled 0x00000000 -#define plb0_acr_hbu_enabled 0x08000000 -#define plb0_acr_rdp_mask 0x06000000 -#define plb0_acr_rdp_disabled 0x00000000 -#define plb0_acr_rdp_2deep 0x02000000 -#define plb0_acr_rdp_3deep 0x04000000 -#define plb0_acr_rdp_4deep 0x06000000 -#define plb0_acr_wrp_mask 0x01000000 -#define plb0_acr_wrp_disabled 0x00000000 -#define plb0_acr_wrp_2deep 0x01000000

-#define plb0_besrl (PLB_ARBITER_BASE+ 0x02) -#define plb0_besrh (PLB_ARBITER_BASE+ 0x03) -#define plb0_bearl (PLB_ARBITER_BASE+ 0x04) -#define plb0_bearh (PLB_ARBITER_BASE+ 0x05) -#define plb0_ccr (PLB_ARBITER_BASE+ 0x08)

-#define plb1_acr (PLB_ARBITER_BASE+ 0x09) -#define plb1_acr_ppm_mask 0xF0000000 -#define plb1_acr_ppm_fixed 0x00000000 -#define plb1_acr_ppm_fair 0xD0000000 -#define plb1_acr_hbu_mask 0x08000000 -#define plb1_acr_hbu_disabled 0x00000000 -#define plb1_acr_hbu_enabled 0x08000000 -#define plb1_acr_rdp_mask 0x06000000 -#define plb1_acr_rdp_disabled 0x00000000 -#define plb1_acr_rdp_2deep 0x02000000 -#define plb1_acr_rdp_3deep 0x04000000 -#define plb1_acr_rdp_4deep 0x06000000 -#define plb1_acr_wrp_mask 0x01000000 -#define plb1_acr_wrp_disabled 0x00000000 -#define plb1_acr_wrp_2deep 0x01000000

-#define plb1_besrl (PLB_ARBITER_BASE+ 0x0A) -#define plb1_besrh (PLB_ARBITER_BASE+ 0x0B) -#define plb1_bearl (PLB_ARBITER_BASE+ 0x0C) -#define plb1_bearh (PLB_ARBITER_BASE+ 0x0D)

/* Pin Function Control Register 1 */ #define SDR0_PFC1 0x4101 #define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */ @@ -742,7 +695,7 @@ #define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */ #define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */

-#endif /* 440EP || 440GR || 440EPX || 440GRX */ +#endif /* 440EP || 440GR || 440EPX || 440GRX */

/*-------------------------------------------------------------------------

| L2 Cache

diff --git a/include/ppc4xx.h b/include/ppc4xx.h index 1d06da8..9dabeee 100644 --- a/include/ppc4xx.h +++ b/include/ppc4xx.h @@ -45,6 +45,66 @@ #define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */ #endif

+/* PLB4 CrossBar Arbiter Core supported across PPC4xx families */ +#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \

• defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
• defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
• defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
• defined(CONFIG_405EX)

+#define CONFIG_PLB4_CROSSBAR_ARBITER_CORE /*PLB4 CrossBar Arbiter Core */ +#endif

+#ifdef CONFIG_PLB4_CROSSBAR_ARBITER_CORE

+#define PLB_ARBITER_BASE 0x80

+#define plb0_revid (PLB_ARBITER_BASE+ 0x00) +#define plb0_acr (PLB_ARBITER_BASE+ 0x01) +#define plb0_acr_ppm_mask 0xF0000000 +#define plb0_acr_ppm_fixed 0x00000000 +#define plb0_acr_ppm_fair 0xD0000000 +#define plb0_acr_hbu_mask 0x08000000 +#define plb0_acr_hbu_disabled 0x00000000 +#define plb0_acr_hbu_enabled 0x08000000 +#define plb0_acr_rdp_mask 0x06000000 +#define plb0_acr_rdp_disabled 0x00000000 +#define plb0_acr_rdp_2deep 0x02000000 +#define plb0_acr_rdp_3deep 0x04000000 +#define plb0_acr_rdp_4deep 0x06000000 +#define plb0_acr_wrp_mask 0x01000000 +#define plb0_acr_wrp_disabled 0x00000000 +#define plb0_acr_wrp_2deep 0x01000000

+#define plb0_besrl (PLB_ARBITER_BASE+ 0x02) +#define plb0_besrh (PLB_ARBITER_BASE+ 0x03) +#define plb0_bearl (PLB_ARBITER_BASE+ 0x04) +#define plb0_bearh (PLB_ARBITER_BASE+ 0x05) +#define plb0_ccr (PLB_ARBITER_BASE+ 0x08)

+#define plb1_acr (PLB_ARBITER_BASE+ 0x09) +#define plb1_acr_ppm_mask 0xF0000000 +#define plb1_acr_ppm_fixed 0x00000000 +#define plb1_acr_ppm_fair 0xD0000000 +#define plb1_acr_hbu_mask 0x08000000 +#define plb1_acr_hbu_disabled 0x00000000 +#define plb1_acr_hbu_enabled 0x08000000 +#define plb1_acr_rdp_mask 0x06000000 +#define plb1_acr_rdp_disabled 0x00000000 +#define plb1_acr_rdp_2deep 0x02000000 +#define plb1_acr_rdp_3deep 0x04000000 +#define plb1_acr_rdp_4deep 0x06000000 +#define plb1_acr_wrp_mask 0x01000000 +#define plb1_acr_wrp_disabled 0x00000000 +#define plb1_acr_wrp_2deep 0x01000000

+#define plb1_besrl (PLB_ARBITER_BASE+ 0x0A) +#define plb1_besrh (PLB_ARBITER_BASE+ 0x0B) +#define plb1_bearl (PLB_ARBITER_BASE+ 0x0C) +#define plb1_bearh (PLB_ARBITER_BASE+ 0x0D)

I would really prefer to have uppercase defines here. I know that this is not your "invention" but still we should probably clean this up now, that we are busy with these PLB arbiter defines. So could you please change those defines to uppercase? Thanks.

Please address the comments above and re-submit. Thanks.

Best regards, Stefan

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