From: Ye Li ye.li@nxp.com
When M33 is LPAV owner in dual boot, DDR, PCC5, CGC2 won't be reset during APD reset. So no need to init DDR again after reboot, but need to reconfigure the PLL4 PFD/PFDDIV/LPAV NIC etc, because kernel may change or disable some of them.
Reviewed-by: Peng Fan peng.fan@nxp.com Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/include/asm/arch-imx8ulp/cgc.h | 2 +- arch/arm/mach-imx/imx8ulp/cgc.c | 20 +++++++++++--------- arch/arm/mach-imx/imx8ulp/clock.c | 2 +- board/freescale/imx8ulp_evk/spl.c | 12 ++++++++++-- 4 files changed, 23 insertions(+), 13 deletions(-)
diff --git a/arch/arm/include/asm/arch-imx8ulp/cgc.h b/arch/arm/include/asm/arch-imx8ulp/cgc.h index e45f04624d..83a246b15a 100644 --- a/arch/arm/include/asm/arch-imx8ulp/cgc.h +++ b/arch/arm/include/asm/arch-imx8ulp/cgc.h @@ -150,7 +150,7 @@ void cgc1_pll3_init(ulong freq); void cgc1_pll2_init(ulong freq); void cgc1_soscdiv_init(void); void cgc1_init_core_clk(ulong freq); -void cgc2_pll4_init(void); +void cgc2_pll4_init(bool pll4_reset); void cgc2_ddrclk_config(u32 src, u32 div); void cgc2_ddrclk_wait_unlock(void); u32 cgc1_sosc_div(enum cgc_clk clk); diff --git a/arch/arm/mach-imx/imx8ulp/cgc.c b/arch/arm/mach-imx/imx8ulp/cgc.c index 494ddb0f32..ccd977f1a5 100644 --- a/arch/arm/mach-imx/imx8ulp/cgc.c +++ b/arch/arm/mach-imx/imx8ulp/cgc.c @@ -187,7 +187,7 @@ void cgc1_pll3_init(ulong freq) } }
-void cgc2_pll4_init(void) +void cgc2_pll4_init(bool pll4_reset) { /* Disable PFD DIV and clear DIV */ writel(0x80808080, &cgc2_regs->pll4div_pfd0); @@ -196,16 +196,18 @@ void cgc2_pll4_init(void) /* Gate off and clear PFD */ writel(0x80808080, &cgc2_regs->pll4pfdcfg);
- /* Disable PLL4 */ - writel(0x0, &cgc2_regs->pll4csr); + if (pll4_reset) { + /* Disable PLL4 */ + writel(0x0, &cgc2_regs->pll4csr);
- /* Configure PLL4 to 528Mhz and clock source from SOSC */ - writel(22 << 16, &cgc2_regs->pll4cfg); - writel(0x1, &cgc2_regs->pll4csr); + /* Configure PLL4 to 528Mhz and clock source from SOSC */ + writel(22 << 16, &cgc2_regs->pll4cfg); + writel(0x1, &cgc2_regs->pll4csr);
- /* wait for PLL4 output valid */ - while (!(readl(&cgc2_regs->pll4csr) & BIT(24))) - ; + /* wait for PLL4 output valid */ + while (!(readl(&cgc2_regs->pll4csr) & BIT(24))) + ; + }
/* Enable all 4 PFDs */ setbits_le32(&cgc2_regs->pll4pfdcfg, 18 << 0); /* 528 */ diff --git a/arch/arm/mach-imx/imx8ulp/clock.c b/arch/arm/mach-imx/imx8ulp/clock.c index 7c45a717be..cc13ccd5ea 100644 --- a/arch/arm/mach-imx/imx8ulp/clock.c +++ b/arch/arm/mach-imx/imx8ulp/clock.c @@ -101,7 +101,7 @@ void init_clk_ddr(void) writel(0xc0000000, PCC5_LPDDR4_ADDR);
/* enable pll4 and ddrclk*/ - cgc2_pll4_init(); + cgc2_pll4_init(true); cgc2_ddrclk_config(4, 1);
/* enable ddr pcc */ diff --git a/board/freescale/imx8ulp_evk/spl.c b/board/freescale/imx8ulp_evk/spl.c index d3cdad2d76..e6949b5e43 100644 --- a/board/freescale/imx8ulp_evk/spl.c +++ b/board/freescale/imx8ulp_evk/spl.c @@ -24,8 +24,16 @@ DECLARE_GLOBAL_DATA_PTR;
void spl_dram_init(void) { - init_clk_ddr(); - ddr_init(&dram_timing); + /* Reboot in dual boot setting no need to init ddr again */ + bool ddr_enable = pcc_clock_is_enable(5, LPDDR4_PCC5_SLOT); + + if (!ddr_enable) { + init_clk_ddr(); + ddr_init(&dram_timing); + } else { + /* reinit pfd/pfddiv and lpavnic except pll4*/ + cgc2_pll4_init(false); + } }
u32 spl_boot_device(void)