On 12/2/2023 3:03 AM, Reid Tonking wrote:
From: Apurva Nandan a-nandan@ti.com
This virtual clock mux configuration enables the use of dynamic frequency scaling on A72 clock ID 202 by setting up the required register.
IMO, dynamic frequency scaling should be supported without this patch. But this patch allows to set freq at different rates other than fixed division. I request to update commit message. Rest LGTM
Signed-off-by: Apurva Nandan a-nandan@ti.com Signed-off-by: Reid Tonking reidt@ti.com
arch/arm/dts/k3-j7200-r5-common-proc-board.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts index f0a73605020..018faaa13b6 100644 --- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts @@ -24,7 +24,8 @@ <&k3_pds 4 TI_SCI_PD_EXCLUSIVE>; resets = <&k3_reset 202 0>; clocks = <&k3_clks 61 1>;
assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>;
assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>, <&k3_clks 323 0>;assigned-clock-parents= <0>, <0>, <&k3_clks 323 2>;