The original code only supported using 1 TSEC port in SGMII mode using an internal TBI PHY. Additionally, the TBI internal PHY was being accessed at the same register offset as the external PHY for the given TSEC port. This hardwiring of the TBI PHY register address based on external PHY address will break in many hardware configurations.
Signed-off-by: Peter Tyser ptyser@xes-inc.com ---
The above limitations were noticed on an mpc8572-based board with 2 sgmii interfaces with external PHYs. Both external PHYs are connected to the MDIO interface of TSEC1 which caused TSEC2 to be non functional since writes to TSEC2's TBI PHY were actually going to TSEC1's TBI PHY.
Due to a hardware limitations I've only been able to test TSEC2's functionality for what its worth.
drivers/net/tsec.c | 15 +++++++++------ include/tsec.h | 2 +- 2 files changed, 10 insertions(+), 7 deletions(-)
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index f81211a..38d4214 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -283,11 +283,13 @@ uint tsec_local_mdio_read(volatile tsec_t *phyregs, uint phyid, uint regnum) /* Configure the TBI for SGMII operation */ static void tsec_configure_serdes(struct tsec_private *priv) { - tsec_local_mdio_write(priv->phyregs, CFG_TBIPA_VALUE, TBI_ANA, + /* Access TBI PHY registers at given TSEC register offset as opposed to the + * offset used for external PHY/MII accesses */ + tsec_local_mdio_write(priv->regs, priv->regs->tbipa, TBI_ANA, TBIANA_SETTINGS); - tsec_local_mdio_write(priv->phyregs, CFG_TBIPA_VALUE, TBI_TBICON, + tsec_local_mdio_write(priv->regs, priv->regs->tbipa, TBI_TBICON, TBICON_CLK_SELECT); - tsec_local_mdio_write(priv->phyregs, CFG_TBIPA_VALUE, TBI_CR, + tsec_local_mdio_write(priv->regs, priv->regs->tbipa, TBI_CR, TBICR_SETTINGS); }
@@ -301,11 +303,12 @@ static int init_phy(struct eth_device *dev) struct phy_info *curphy; volatile tsec_t *phyregs = priv->phyregs; volatile tsec_t *regs = priv->regs; + static int tbi_offset = 0;
- /* Assign a Physical address to the TBI */ - regs->tbipa = CFG_TBIPA_VALUE; - phyregs->tbipa = CFG_TBIPA_VALUE; + /* Assign a unique physical address to the internal TBI PHY */ + regs->tbipa = CFG_TBIPA_VALUE + tbi_offset; asm("sync"); + tbi_offset++;
/* Reset MII (due to new addresses) */ priv->phyregs->miimcfg = MIIMCFG_RESET; diff --git a/include/tsec.h b/include/tsec.h index 2db4deb..69f068e 100644 --- a/include/tsec.h +++ b/include/tsec.h @@ -110,7 +110,7 @@ #define miim_read -1
#ifndef CFG_TBIPA_VALUE - #define CFG_TBIPA_VALUE 0x1f + #define CFG_TBIPA_VALUE 0x10 #endif #define MIIMCFG_INIT_VALUE 0x00000003 #define MIIMCFG_RESET 0x80000000