On Mon, Apr 23, 2018 at 8:27 PM, Lothar Felten lothar.felten@gmail.com wrote:
Add support for the GMAC found in the Allwinner R40/V40 SoC.
The R40 GMAC interface is not controlled by the syscon register but has a separate configuration register in the CCU. The clock gate and reset bits are in a different register compared to the other SoCs supported by this driver. The diver uses the -gmac suffix for the R40 because the R40 also has a different 100 MBit MAC (EMAC).
Signed-off-by: Lothar Felten lothar.felten@gmail.com
drivers/net/sun8i_emac.c | 69 +++++++++++++++++++++++++++++++++--------------- 1 file changed, 47 insertions(+), 22 deletions(-)
diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c index b6e5dafe83..83844a1d40 100644 --- a/drivers/net/sun8i_emac.c +++ b/drivers/net/sun8i_emac.c @@ -68,6 +68,8 @@
#if defined(CONFIG_MACH_SUNXI_H3_H5) #define SUN8I_GPD8_GMAC 2 +#elif defined(CONFIG_MACH_SUN8I_R40) +#define SUN8I_GPD8_GMAC 5
Can be done through driver_data?
#else #define SUN8I_GPD8_GMAC 4 #endif @@ -99,6 +101,7 @@ DECLARE_GLOBAL_DATA_PTR; enum emac_variant { A83T_EMAC = 1, H3_EMAC,
R40_GMAC, A64_EMAC,};
@@ -279,6 +282,9 @@ static int sun8i_emac_set_syscon(struct emac_eth_dev *priv) int ret; u32 reg;
if (priv->variant == R40_GMAC)return 0;reg = readl(priv->sysctl_reg + 0x30); if (priv->variant == H3_EMAC) {@@ -630,11 +636,25 @@ static void sun8i_emac_board_setup(struct emac_eth_dev *priv) } #endif
+#ifdef CONFIG_MACH_SUN8I_R40
/* Set clock gating for emac */setbits_le32(&ccm->ahb_reset1_cfg, BIT(AHB_RESET_OFFSET_GMAC));/* De-assert EMAC */setbits_le32(&ccm->ahb_gate1, BIT(AHB_GATE_OFFSET_GMAC));/* Select RGMII for R40 */setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |CCM_GMAC_CTRL_GPIT_RGMII);setbits_le32(&ccm->gmac_clk_cfg,CCM_GMAC_CTRL_TX_CLK_DELAY(CONFIG_GMAC_TX_DELAY));+#else
Can be done through driver_data variant?
Jagan.