This patch adds clock gating driver for MediaTek MIPS platform
Signed-off-by: Weijie Gao weijie.gao@mediatek.com --- drivers/clk/Kconfig | 8 ++++ drivers/clk/Makefile | 1 + drivers/clk/clk-mtmips-cg.c | 63 ++++++++++++++++++++++++++++ include/dt-bindings/clk/mt7628-clk.h | 31 ++++++++++++++ 4 files changed, 103 insertions(+) create mode 100644 drivers/clk/clk-mtmips-cg.c create mode 100644 include/dt-bindings/clk/mt7628-clk.h
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 95fe0aea2c..0762a42476 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -160,4 +160,12 @@ config SANDBOX_CLK_CCF Enable this option if you want to test the Linux kernel's Common Clock Framework [CCF] code in U-Boot's Sandbox clock driver.
+config CLK_MTMIPS_GATE + bool "Enable clock gating driver for MediaTek MIPS platform" + depends on CLK && ARCH_MTMIPS + default y + help + Enable clock gating driver for MediaTek MIPS platform. + This driver supports only clock enable and disable. + endmenu diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 68aabe1ca9..353974d784 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -26,6 +26,7 @@ obj-$(CONFIG_CLK_BOSTON) += clk_boston.o obj-$(CONFIG_CLK_EXYNOS) += exynos/ obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o obj-$(CONFIG_CLK_MPC83XX) += mpc83xx_clk.o +obj-$(CONFIG_CLK_MTMIPS_GATE) += clk-mtmips-cg.o obj-$(CONFIG_CLK_OWL) += owl/ obj-$(CONFIG_CLK_RENESAS) += renesas/ obj-$(CONFIG_CLK_SIFIVE) += sifive/ diff --git a/drivers/clk/clk-mtmips-cg.c b/drivers/clk/clk-mtmips-cg.c new file mode 100644 index 0000000000..0221d95aed --- /dev/null +++ b/drivers/clk/clk-mtmips-cg.c @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 MediaTek Inc. All Rights Reserved. + * + * Author: Weijie Gao weijie.gao@mediatek.com + */ + +#include <common.h> +#include <clk-uclass.h> +#include <dm.h> +#include <asm/io.h> + +struct mtmips_clk_gate_priv { + void __iomem *base; +}; + +static int mtmips_clk_gate_enable(struct clk *clk) +{ + struct mtmips_clk_gate_priv *priv = dev_get_priv(clk->dev); + + setbits_32(priv->base, BIT(clk->id)); + + return 0; +} + +static int mtmips_clk_gate_disable(struct clk *clk) +{ + struct mtmips_clk_gate_priv *priv = dev_get_priv(clk->dev); + + clrbits_32(priv->base, BIT(clk->id)); + + return 0; +} + +const struct clk_ops mtmips_clk_gate_ops = { + .enable = mtmips_clk_gate_enable, + .disable = mtmips_clk_gate_disable, +}; + +static int mtmips_clk_gate_probe(struct udevice *dev) +{ + struct mtmips_clk_gate_priv *priv = dev_get_priv(dev); + + priv->base = (void __iomem *)dev_remap_addr_index(dev, 0); + if (!priv->base) + return -EINVAL; + + return 0; +} + +static const struct udevice_id mtmips_clk_gate_ids[] = { + { .compatible = "mediatek,mtmips-clk-gate" }, + { } +}; + +U_BOOT_DRIVER(mtmips_clk_gate) = { + .name = "mtmips-clk-gate", + .id = UCLASS_CLK, + .of_match = mtmips_clk_gate_ids, + .probe = mtmips_clk_gate_probe, + .priv_auto_alloc_size = sizeof(struct mtmips_clk_gate_priv), + .ops = &mtmips_clk_gate_ops, +}; diff --git a/include/dt-bindings/clk/mt7628-clk.h b/include/dt-bindings/clk/mt7628-clk.h new file mode 100644 index 0000000000..6784d6e50b --- /dev/null +++ b/include/dt-bindings/clk/mt7628-clk.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 MediaTek Inc. + * + * Author: Weijie Gao weijie.gao@mediatek.com + */ + +#ifndef _DT_BINDINGS_MT7628_CLK_H_ +#define _DT_BINDINGS_MT7628_CLK_H_ + +#define MT7628_PWM_CLK 31 +#define MT7628_SDXC_CLK 30 +#define MT7628_CRYPTO_CLK 29 +#define MT7628_MIPS_CNT_CLK 28 +#define MT7628_PCIE_CLK 26 +#define MT7628_UPHY_CLK 25 +#define MT7628_ETH_CLK 23 +#define MT7628_UART2_CLK 20 +#define MT7628_UART1_CLK 19 +#define MT7628_SPI_CLK 18 +#define MT7628_I2S_CLK 17 +#define MT7628_I2C_CLK 16 +#define MT7628_GDMA_CLK 14 +#define MT7628_PIO_CLK 13 +#define MT7628_UART0_CLK 12 +#define MT7628_PCM_CLK 11 +#define MT7628_MC_CLK 10 +#define MT7628_INT_CLK 9 +#define MT7628_TIMER_CLK 8 + +#endif /* _DT_BINDINGS_MT7628_CLK_H_ */